JPH03262052A - Information processor - Google Patents

Abstract

PURPOSE:To solve the problem of response delay of a signal due to buffer skew and to keep the normal input/output operation between a memory and a processor by incorporating a request signal output means for the purpose of quickly responding to the main processor side with a wait cycle request signal. CONSTITUTION:A data processor 4 incorporates an access discriminating means 41 which discriminates the access to a memory system 1 and wait request signal output means 42 and 43 which output the wait request signal before the wait request signal in a memory read/write cycle is inputted to the main processor 4 from the memory system 1 through an extension bus 3 at the time of discriminating the access. Thus, the main processor 4 performs the processing for the wait request at a requested timing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device that inputs and outputs data between a main processor and a memory connected to a system bus extended from the main processor. It is something.

(Prior Art) Figure 2 is an example of a block diagram showing a conventional information processing device that connects memory to an expansion bus and performs data input/output. This is a memory system section that is extended outside the processor block (20) of section (2).

The memory system unit (1) decodes the address input from the main processor unit (2) via the memory element, memory control unit (10), and external expansion cable (3), and issues an access request to itself. It has a built-in address decoder (11) that outputs a select signal (CS) to the memory when determining an access request.

A conventional device will be explained using figures. Main processor section (2
), when trying to input/output data from the memory section (1
) is output and output to the memory section (1) through the external expansion cable (3). In the memory unit (1), the address is decoded by the address decoder (11), and if it is an input/output request for itself, a select signal (C
5), and the memory control block (lO) generates a memory read/write cycle wait request signal (WR in the figure).
Q) is returned to the processor block unit (20) of the main processor unit (2) via the external expansion cable (3). The wait request signal is extended until the end of the wait request signal to cover the memory access time which is slower than the processing time of the processor block section (2) and perform input/output operations to the memory.

[Problem to be solved by the invention]

Conventional devices are configured as described above, so when an attempt is made to expand the bus and add a memory system, the wait cycle request signal is delayed due to the time delay caused by buffer skew, etc. There was a problem in that it was not possible to meet the requested timing.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an information processing device that can solve the delay in response to a wait request signal caused by system bus expansion.

(Means for Solving the Problem) An information processing device according to the present invention extends a system bus in a data processing device including a main processor to the outside by an external bus, and the expansion bus is accessed by the main processor. In the device to which a memory system is connected, access determination means for determining access to the memory system is provided in the data processing device;
It has a built-in wait request signal output means that outputs a wait request signal until a wait request signal for a memory read or write cycle is input from the memory system to the main processor via the expansion bus at the time of access determination. be.

[Effect]

According to this invention, the access determination means determines that the main processor has sent a data access request to the memory system via the expansion bus, and the wait request signal output means outputs the wait request signal to the main processor within the response time required by the main processor. Since a wait request signal is input manually from the memory system and then a wait request signal is input manually from the memory system via the expansion bus, the main processor can process the wait request at the required timing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a memory system section that is extended to the outside of the main processor section (4) via an external expansion cable (3). The main processor unit (4) includes the main processor unit (2) shown in FIG. 2 in the explanation of the prior art.
In addition to this function, there is a comparator unit (41) that compares the address output from the processor block with preset conditions, and a timer (42) that outputs a WRQ signal for a certain period of time when it is determined that the comparison results match. , the timer (42
) and external expansion cable (3)
W is input from the memory system unit (1) via
It has a built-in OR gate (43) that takes the logical sum of the RQ signals and outputs the WRQ signal to the processor block (40).

The address of the memory unit (1) to which data is to be output by the main processor unit (4) (1 in the example shown)
111°) is output and output to the memory section (1) through the external expansion cable (3). At the same time, a comparison circuit (comparator) (41) provided on the main processor section (4) compares the output address with a preset value (1111° in the example shown). Since both are equal, this access is to external memory. Therefore, the WRQ signal is returned to the processor block section (40). On the other hand, in the memory unit (1), the address is decoded by the address decoder (41), and since this is an input/output request for itself, a select signal C5 is generated and output to the memory control block (lO). returns the wait cycle request signal WRQ to the processor block section (40) via the external expansion bus (3). Normally, WR output from the comparator (41) of the main processor section (4) due to buffer skew, etc.
The Q signal is the WR from the memory control block (lO).
The processor block (4
By installing this comparator (41), the WRQ signal can be returned within the response time required by the processor block (40).

While the IRQ signal is being returned from the comparator (41), the IRQ signal is returned from the memory section (1) to the main processor section (4).
Since the IRQ signal is output by the comparator (41) of ), the logical sum with this IRQ signal is the OR gate (
43). Next, a timer (42) connected to the output of the comparator (41) prevents the IRQ signal output from the comparator (41) from being output after a predetermined set time. The time set by this timer is calculated in advance based on buffer skew and the like when accessing the memory section (1), and is set with a sufficient margin. This WRQ signal allows the processor block section (40) to extend the human output cycle of the corresponding data, thereby allowing normal data input/output to and from the memory section (1).

In the above example, a power pull-up is used to set the comparison conditions of the comparator section, but if this section is equipped with a mechanism such as a dip switch that can easily change the settings, it can be connected to an external expansion bus. Even if the address of the memory section to be stored changes, it is possible to cope with the change.

〔Effect of the invention〕

As described above, according to the present invention, since the wait cycle request signal is made to respond to the main processor side as soon as possible, the problem of signal response delay due to buffer skew is solved, and normal input/output between memory and processor is achieved. It has the effect of maintaining operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional information processing apparatus. (1) is a memory system section, (2) is a main processor section, (3) is an external expansion cable, (4) is a main processor section equipped with an address comparison circuit, (40) is a processor block, and (41) is a The comparator (42) is a timer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A system bus in a data processing device incorporating a main processor is extended to the outside by an external bus, and a memory system accessed by the main processor is connected to the expansion bus, wherein the memory system is connected to the memory system in the data processing device. access determination means for determining access to the memory; and outputting a wait request signal until a wait request signal for a memory read or write cycle is inputted from the memory system to the main processor via the expansion bus at the time of access determination. An information processing device characterized by having a built-in wait request signal output means.