JPS6244667B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wait signal prefetch circuit for a high-speed arithmetic element.

High-speed arithmetic elements (such as those provided by AMD) are used in microcomputer systems, etc.
When using AM9511), as the processing speed of the host computer (hereinafter simply referred to as the CPU) increases, the CPU cannot accept wait signals to keep the CPU in a wait state until the processing of high-speed arithmetic elements is completed. The CPU advances processing before the operation of the high-speed arithmetic element is completed, and the high-speed arithmetic element has the disadvantage of not being able to operate normally.

FIG. 1 shows a conventional configuration using the above-mentioned high-speed arithmetic element, and FIG. 2 is a time chart showing its operation. In Figure 1, 1 is the CPU,
2 is a high-speed arithmetic element, 3 is a chip select circuit,
AD is address bus, DT is data bus,
indicates a read signal, indicates a write signal, and indicates a chip select signal. Note that FIG. 2A shows a read operation, and FIG. 2B shows a write operation.

However, as shown in Figure 2 A, the clock period
In synchronization with the falling edge of the _T2 clock signal CLK.
When CPU 1 executes reading and becomes L level, in response to this, a wait signal is output from high speed arithmetic element 2 and becomes "L". However, some time is required before this wait signal is output, and the time t _RP is about 150 [n sec] at maximum, although there are variations depending on the device. Now, for example, set the CPU clock frequency to 3 [M].
Hz], the half period of the clock t _w is approximately 166
[n sec], and the time t _RYS from the generation of the wait signal to the rising edge of the clock signal CLK during the clock period _T2 is approximately 16 [n sec] (=t _w −t _R
There is only _P ). In addition, in order for CPU 1 to consider this as a wait signal, the ready set up interval must be approximately 110 [n] after the rising edge of clock signal CLK.
sec] must become "L" before t RYS =16 [n sec], and as in this example, t _RYS = 16 [n sec] cannot be accepted as a wait signal.
The same thing can be said about the write operation shown in FIG. 2B.

The above malfunctions can be resolved by lowering the CPU clock frequency, but operating a CPU capable of high-speed processing at a low clock frequency is not only uneconomical, but also reduces processing speed. This is not a good idea.

The present invention has been proposed in view of the above points, and it sends a separate wait signal to the CPU before the high-speed arithmetic element outputs the wait signal, thereby allowing the high-speed arithmetic element to operate normally without lowering the clock frequency of the CPU. It is an object of the present invention to provide a waiting signal prefetching circuit for a high-speed arithmetic element that enables operation.

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 3 is a block diagram showing the state of use of the present invention, and parts common to the conventional example shown in FIG. 1 are given the same reference numerals. In FIG. 3, numeral 4 indicates a wait signal prefetch circuit, and its specific configuration is shown in FIGS. 4 and 6.

FIG. 4 shows a first example of the present invention, and FIG. 5 is a time chart showing its operation. In Figure 4, ALE is an address latch enable signal, and in a type of CPU that shares the data bus as part of the address bus (for example, the lower 8 bits), the contents of the data bus can be taken into the address latch as an address. It is intended to give instructions. Since this address latch enable signal ALE is output prior to a read signal or a write signal, it is used in the present invention as a warning signal for a read or write operation.

Now, to explain the configuration of the wait signal prefetch circuit 4, the address latch enable signal of the CPU 1 is
ALE, clock signal CLK is the detection/holding circuit 41
The Q output terminal of flip-flop D1 is connected to the clock input terminals of flip-flops _{D1 and D2} that constitute the flip-flop.
The output terminal of flip-flop _D2 is connected to the D input terminal of flip-flop _D2 and the clear input terminal of flip-flop _D1 , respectively. Further, the D input terminal and preset input terminal of flip-flop _D1 , and the clear input terminal and preset input terminal of flip-flop _D2 are connected to the power supply _Vcc , respectively.
The flip-flops D ₁ and D ₂ are D flip-flops, which read the contents of the D input and output the Q output at the rising edge of the clock. On the other hand, the chip select signal of the chip select circuit 3 is applied to both inputs of the gate _G1 constituting the logic circuit 42, and the output terminal of this gate _G1 is
The Q of the flip-flop _D2 is connected to one input terminal of the gate G2, and _the Q of the flip-flop _D2 is connected to the other input terminal of the gate G2.
An output terminal, that is, an output terminal of the detection/holding circuit 41 is connected.

The wait signal of high-speed arithmetic element 2 is connected to one input terminal of gate _G3 , and
The output terminal of gate G ₂ is connected to the other input terminal of G ₃ , the output terminal of gate G ₃ is connected to both input terminals of gate G ₄ , and the output terminal of gate G ₄ is connected to the ready signal ready. (The waiting signal is
To send a ready signal (from the CPU's perspective)
Connected to the ready input terminal of CSU1.

Next, the operation will be explained according to the time chart shown in FIG. Now, when the CPU 1 attempts to perform a read or write operation on the high-speed arithmetic element 2, the address latch enable signal ALE is output during the clock period _T1 before the read signal or write signal is sent. When the address latch enable signal ALE rises, the flip-flop _D1 of the detection/holding circuit 41 connects to the power supply V connected to its D input terminal.
Read _CC as “H” level and output its Q output
_Q1 becomes “H”. After half a period, flip-flop D ₂ is activated by the rising edge of clock signal CLK.
reads the Q output Q ₁ of the flip-flop D ₁ and sets its own Q output Q ₂ to “H”, and clears the flip-flop D ₁ by the output that has become “L”. On the other hand, the logical operation of the logic circuit 42 composed of gates G ₁ , G ₂ , G ₃ , and G ₄ is as follows: ready= ₂・+ −(1) (where, CS=CS, pause=pause) ), ready signal ready = “L”, Q ₂ =
When the conditions for "H" are met, it changes to "L". In addition,
The reason why the chip select signal of the chip select circuit 3 is used as one of the conditions is that even if a read or write operation is executed, it may not be for the high-speed arithmetic element 2. is executed and the high-speed arithmetic element 2 is selected, the ready signal ready is set to "L" as a wait signal.

Next, in clock period _T2, the read signal or write signal becomes "L", and in response to this, after time _tRP , high-speed arithmetic element 2 sets the wait signal to "L", but before entering clock period _T2 . The ready signal ready has already become "L", and the CPU enters the wait state without waiting for the wait signal from the high-speed arithmetic element 2. Furthermore, with the rise of the clock signal CLK during the clock period _T2 , the flip-flop _D2 reads the Q output _Q1 (already "L" at this time) of the flip-flop D.
The Q output _Q2 of _D2 turns to "L". However, at this point, the wait signal from the high-speed arithmetic element 2 has become "L", and if Q ₂ = "L" in the above equation (1), then ready = -(2), and the wait signal from the high-speed arithmetic element 2 has become "L". signal is direct
It will be sent to the CPU. Therefore, although not shown, when the high-speed arithmetic element 2 completes processing several cycles later, the wait signal becomes "H".
The wait state is released from the immediately following clock period.

Address latch enable signal as above
This is because the read or write operation is known in advance by ALE, and after the address is determined and the CPU 1 is enabled to accept the wait signal, the ready signal ready is set to "L" as the wait signal immediately. , the time until the rise of the clock signal CLK has been extended to t _RYS ', which is sufficient to cover the ready setup interval.
The high-speed arithmetic element 2 can be made to operate normally.

Next, Figure 6 shows the second example, in which the CPU
This can deal with the case where the clock frequency of 1 becomes even higher.

That is, as the clock frequency of the CPU 1 becomes higher, each clock period becomes shorter, but the time t _RP from when the read signal (or write signal) is output until the wait signal is output from the high-speed arithmetic element 2
(or t _WP ) does not change, so the clock period
This causes an inconvenience that the wait signal does not become "L" before the rise of the clock signal CLK at _T2 . Therefore, the ready signal expressed by the above equation (1)
ready remains "H" from when the signal Q ₂ becomes "L" at the rising edge of the clock signal CLK during the clock period T ₂ until the wait signal of the high-speed arithmetic element 2 becomes "L", and the CPU 1 waits. It does not become a state. Therefore, in this second example, the one-shot multi OM stretches the signal Q ₂ and connects the gate G ₂
The above malfunctions are resolved by adding Its configuration is that a one-shot multi OM is inserted between the Q output terminal of flip-flop D ₂ and gate _{G 2} in the first example shown in FIG _. The Yotsuto Multi OM constitutes the detection/holding circuit 41', and the other configurations are the same as in the first example. In this case, the ready signal ready is a one shot multi OM.
Letting the output of Q ₃ be expressed by the following formula ready= ₃・+ −(3).

FIG. 7 is a time chart showing the operation. As mentioned above, the Q output _Q2 of the flip-flop _D2 turns to "L" by the rising edge of the clock signal CLK during the clock period, but the one-shot multi OM operates due to the rising edge of this signal _Q2 , and its output _Q3 remains “H” until a wait signal is generated from high-speed arithmetic element 2 and it is certain.
is maintained to prevent interruptions in the ready signal.

Therefore, this example has the advantage that even if the processing speed of the CPU 1 becomes faster, the high-speed arithmetic element can operate normally.

As described above, according to the present invention, a read or write operation is detected in advance by the address latch enable signal ALE that appears before a read or write by the CPU, and the address is determined and the CPU accepts the wait signal. Immediately after enabling the CPU, the ready signal ready is set to "L" as a wait signal, and after the wait signal is obtained from the high-speed arithmetic element, the wait signal is given using this signal. This has the effect that requests and cancellations of states can be performed smoothly and reliably, and high-speed arithmetic elements can be operated normally.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the conventional configuration, Fig. 2 A and B are time charts showing the operation of the conventional example, Fig. 3 is a block diagram showing the usage state of the present invention, and Fig. 4
The figure is a specific circuit diagram of the first example of the present invention, Figure 5 is a time chart showing the same operation, and Figure 6 is the second example.
A specific circuit diagram of the example shown in FIG. 7 is also a time chart showing the operation. 1...CPU, 2...High-speed arithmetic element, 3...Chip select circuit, 4...Waiting signal preemption circuit,
AD...address bus, DT...data bus,
D ₁ , D ₂ ... flip-flop, G ₁ , G ₂ , G ₃ , G ₄
...Gate, 41, 41'...Detection/holding circuit,
42...Logic circuit, OM...One-shot multi.

Claims (1)

[Scope of Claims] 1. In a system comprising a CPU, a high-speed arithmetic element, and a chip select circuit, and configured to drive the high-speed arithmetic element under control of the CPU, generation of an address latch enable signal of the CPU is detected. , a detection/holding circuit consisting of a flip-flop that holds a signal for a certain period of time, a wait signal of the high-speed arithmetic element, a chip select signal of the chip select circuit, and an output of the detection/holding circuit; 1. A wait signal prefetch circuit for a high-speed arithmetic element, comprising a logic circuit that generates a ready signal to the CPU. 2. In a system comprising a CPU, a high-speed arithmetic element, and a chip select circuit, and configured to drive the high-speed arithmetic element under the control of the CPU, generation of an address latch enable signal of the CPU is detected, and the signal is a detection/holding circuit consisting of a flip-flop and a one-shot multi-chip that holds the CPU; 1. A wait signal prefetch circuit for a high-speed arithmetic element, comprising a logic circuit that generates a ready signal to a high-speed arithmetic element.