KR920004987Y1 - Generating circuit for board enable signal - Google Patents

Abstract

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Description

Board Enable Signal Generation Circuit

1 is a circuit diagram of the present invention.

2 is a concrete circuit diagram of the PAL during the first time.

* Explanation of symbols for main parts of the drawings

10: CPU 20: latch portion

30: PAL circuit 40: buffer

50: Bus controller G1: Exclusive Oagate

G2, G3: NAND Gate INV1: Inverter

The present invention relates to a board enable signal and a generation circuit of a multi-board system.

In general, an 80286 CPU hardware system using a microprocessor 80286 is a very fast system with a system clock of 8-10 MHz.

However, the existing low cost memory and input / output components connected to this system are very slow, and in the case of multiboard systems, the existing 80286 bus cycle status decoded signal could malfunction each board active signal.

Conventional M / Enable buffers on each board using M / E even when S1 = 0 and S0 = 0 in 80286 bus cycle status decoding. There was a problem that the data buffer to be present in the high impedance state is enabled due to the signal generated, so that I / O of wrong data occurs or a data bus collision occurs. In addition, the conventional memory read command signal ( ), Memory ride command signal ( ), I / O read command ( ), I / O write command ( ), The signals are generated in the command cycle (Tc), which is the processor clock, which may result in incomplete data input / output.

Therefore, the purpose of the present invention is to provide a data bus buffer for each board and an M / Decodes the signal before sending it to the bus controller and sends it to each board. When the 80286 CPU is in an idle state (S0 and S1 are all low), the 80286 CPU does nothing for memory and I / O. It is to provide a PAL (Programmable Array Logic) circuit to stabilize.

Hereinafter, with reference to the accompanying drawings of the present invention.

1 is a block diagram of the present invention, a bus cycle status (hereinafter referred to as S1, S1) signal and memory / input, output signal (hereinafter M / And an 80286 CPU 10 for controlling a multitasking system, and the S0, S1, M / S0, S1, M / according to the bus controller 50 generating various command signals from the signal and the strobe signal ALE generated from the bus controller 50. A latch 20 for decoding the signal to generate an address signal, and S0, S1, M / inputted from the latch 20; By logically combining the signals, the memory address enable signal ( ) And input and output address enable signals ( And a buffer 40 for storing data according to the output state of the PAL circuit 30.

FIG. 2 is a concrete circuit diagram of the PAL circuit 30 during the first phase, in which an exclusive oar gate G1 for exclusively ORing by inputting S1 and S0 signals and M / Inverter INV1 for inverting the signal, the output of the exclusive oragate G1, and M / Logically combine the signals A first NAND gate G2 for generating a signal, and an output of the exclusive oragate G1 and M / Logically combine the signals The second NAND gate G3 generates a signal.

Based on the above-described configuration will be described the present invention in detail.

In Fig. 1, the bit terminals D0-D15 are used for input and output of data from the 80286 CPU 10.

The 80286 CPU 10 does not have a terminal for directly outputting a command signal. Instead, a command sent from the 80286 CPU 10 to the memory and the I / O is expressed by a 2-bit status signal output from the S0 and S1 terminals. When the 80286 CPU 10 is in a state in which no operation is performed on the memory and I / O (idle state), both S0 and S1 are turned low. The distinction between operations on memory and I / O is M / Distinguished by the output of the terminal. M / Is high, it means that it is operation for memory and M / When is low, it indicates that the operation for I / O is done. S0, S1, M / Decode the signal to create a command signal.

At this time, M / B that activates data bus buffer of each board and each memory and input / output device for reliable data transmission. The signal is decoded before the bus controller 50 signal is generated and transmitted to each board.

In addition, when the CPU 10 is in an idle state in which no operation is performed on the memory and I / O, the above-described conventional malfunction may be prevented by configuring a PAL circuit as shown in FIG.

That is, the L0 and S1 signals are logically combined from the latch 20 using the exclusive oragate G1, and the result is M /. Signal and its inverted signal and logical combination of two NAND gates (G2, G3) respectively And Each board and component can be enabled only when a signal occurs, and the program is as follows.

!, n: inverting

&: And

#: OR

As mentioned above, the improved M / When using an enable signal, the conventional M / Malfunction of data signal from signal usage and the advantage of preventing collision due to enable signal malfunction of data bus, as well as satisfying high speed operation bus system, and saving space by using PAL circuit There is this.

Claims (2)

A multi-board system, comprising: a central processing unit for generating a first and second bus cycle status signals and a memory / input / output signal and controlling a multitask system; A bus controller which generates various command signals, a latch which decodes the first and second bus cycle status signals and a memory / input / output signal according to the strobe signal state generated from the bus controller, and generates an address signal; A programmable array logic circuit for generating a memory address enable signal and an input / output address enable signal by logically combining the first and second bus cycle status signals and the memory / input / output signals inputted from the programmable array logic output; As a buffer to store data according to state Board enable signal generation circuit, characterized in that configured. 2. The apparatus of claim 1, wherein the programmable array logic circuit comprises means for exclusive OR of the first and second bus cycle status signals, and the exclusive OR result is converted into a memory / input / output signal and an inverted signal of the memory / input / output signal. And first and second logic combination means for NAND gating to generate a memory address enable and an input and output enable signal, respectively.