JPH04260958A - Microcomputer - Google Patents

Abstract

PURPOSE:To remove a signal change in an external bus in the case of accessing an internal slave device and to reduce power consumption in the whole system. CONSTITUTION:An address decoder 14 decides which slave device, an external slave device 2 or an internal slave device 5, is accessed by an internal bus master 4 for outputting a signal controlling the device 2 or 5, and at the time of accessing the device 5 based upon the decided result, the status change of a signal controlling the device 2 is inhibited by an AND gate 15 and an output latch 16.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer that can reduce power consumption in a system including external slave devices.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing a system configuration including a conventional microcomputer. In the figure 1
is a microcomputer, and the microcomputer 1 is connected to an external slave device 2 and an external bus master 3 via an external bus 10 including a control signal bus, an address bus, and a data bus. Inside the microcomputer 1, an internal bus master 4 and an internal slave device 5 that output various control signals to an external slave device 2 and an internal slave device 5 are connected via an internal bus 6 including a control signal bus, an address bus, and a data bus. Various control signals output from the internal bus master 4 are temporarily stored in the output buffer 8 via the internal bus 6, and when the microcomputer 1 acquires the bus right to the external bus 10, they are sent to the external device via the output pin 9. It is output to bus 10. An output buffer active signal OBA is applied to the output buffer 8 from the internal bus master 4, and when the microcomputer 1 acquires the bus right, the signal OBA is asserted and the output buffer 8 becomes active during that time.

Next, the access operation of the conventional microcomputer 1 configured as described above will be explained. When the bus mastership of the external bus 10 is transferred from the external bus master 3 to the microcomputer 1, the microcomputer 1 becomes able to access the external slave device 2. When the microcomputer 1 accesses the external slave device 2, the output buffer active signal OBA is first asserted, the output buffer 8 becomes active, and then various control signals from the internal bus master 4 are asserted.
Internal bus 6, output buffer 8, output pin 9, external bus 1
0 to the external slave device 2, and the external slave device 2 is activated. On the other hand, when the microcomputer 1 accesses the internal slave device 5, various control signals from the internal bus master 4 are asserted and output to the internal slave device 5 via the internal bus 6, and the internal slave device 5 is activated. Ru. At this time, the output buffer active signal OBA is asserted in the same way as when accessing the external slave device 2 described above. Therefore, various control signals are also output to the external slave device 2. However, in this case, the various control signals are not valid for the external slave device 2.

0004

As described above, in conventional microcomputers, various control signals are asserted, changed, and activated even when an internal bus master accesses an internal slave device. In other words, there is a problem in that by changing the signal, extra power is consumed to drive the external bus unnecessarily. The present invention has been made to solve these problems, and when accessing an internal slave device, prohibits changes in the state of control signals to the outside, thereby reducing unnecessary power consumption due to signal changes on the external bus. The purpose of the present invention is to provide a microcomputer that can reduce the power consumption of the entire system.

[0005]

[Means for Solving the Problems] In the microcomputer according to the present invention, an access determination means determines whether a bus master accesses an external slave device or an internal slave device, and when a bus master accesses an internal slave device, When a determination is made, the state change of the signal controlling the external slave device is prohibited.

[0006]

[Operation] In the present invention, when the access determination means determines that the bus master accesses the internal slave device, the state change prohibition means inhibits the state change of the signal controlling the external slave device, leaves the signal state as it is, and reduce consumption.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a block diagram showing a system configuration including a microcomputer according to the present invention. In the figure, reference numeral 1 denotes a microcomputer of the present invention, and the microcomputer 1 is connected to an external slave device 2 and an external bus master 3 via an external bus 10 including a control signal bus, an address bus, and a data bus. Inside the microcomputer 1, an internal bus master 4 and an internal slave device 5 that output various control signals to an external slave device 2 and an internal slave device 5 are connected via an internal bus 6 including a control signal bus, an address bus, and a data bus. Various control signals output from the internal bus master 4 are sent to the internal bus 6, and the assertion prohibition section 13 which is the access determination means and state change prohibition means which are the gist of the present invention.
is temporarily stored in the output buffer 8 via the external bus 10.
When the microcomputer 1 acquires the bus right, the data is output to the external bus 10 via the output pin 9. An output buffer active signal OBA is applied to the output buffer 8 from the internal bus master 4, and when the microcomputer 1 acquires the bus right, the signal OBA is asserted and the output buffer 8 becomes active during that time.

It is assumed that the address areas of internal slave device 5 and external slave device 2 are in the same memory space. FIG. 2 is a block diagram showing an example of the configuration of the assertion prohibition unit 13. A timing signal TS determined for each type of control signal and an address signal (hereinafter referred to as source address signal) ADD determined before the timing signal TS are inputted to the assertion prohibition unit 13 from the internal bus master 4, and asserted. The prohibition unit 13 determines whether to access the internal slave device 5 or the external slave device 2 based on the source address signal ADD, and uses the radius result to determine whether the internal bus master 4 is to be accessed.
This prohibits the assertion of control signals from the When the internal bus master 4 accesses the external slave device 2 or the internal slave device 5, this source address signal ADD is outputted with a different address depending on which one is accessed. The source address signal ADD is input to an address decoder 14 serving as access determination means, decoded, and input to one end of an AND gate 15. The other end of the AND gate 15 has a timing signal TS.
is input, and its output is given to the trigger terminal T as a trigger signal of the output latch 16. Further, the control signal is applied to the data terminal D of the output latch 16, and A
The output from the ND gate 15 is output from the output terminal Q at the rising timing of the output. This AND gate 1
5 and the output latch 16 constitute state change inhibiting means.

Address decoder 14 receives source address signal A.
When the DD is for accessing the external slave device 2, it outputs ``H'', and conversely, when it is for accessing the internal slave device 5, it outputs ``L''. Next, the access operation of the slave device of the microcomputer of the present invention configured as described above will be explained. FIG. 3 is a timing chart showing changes in signals of each part of the assertion prohibition unit 13. When the bus mastership of the external bus 10 is transferred from the external bus master 3 to the microcomputer 1 and the internal bus master 4 starts a bus cycle, the source address signal ADD and the timing signal T are sent to the assertion inhibiting section 13.
S is sent.

Various control signals within the microcomputer 1 are generally generated by synchronizing control signals that are previously established with an output timing reference clock. In the assertion inhibiting section 13 as well, the output of the address decoder 14 is determined before the rising edge of the timing signal TS in order to generate a control signal using the output timing reference clock. Therefore, when the bus cycle is an access cycle to the internal slave device 5, the decoding result of the source address signal ADD becomes ■L'', and then the timing signal TS becomes ■
Even if the AND gate 15 becomes ``H'' and activated, the output of the AND gate 15 becomes ``L'', and the trigger terminal T of the output latch 16
Since no trigger signal is input to internal bus master 4,
The control signal from is not output to the external bus 10. In other words, the output buffer active signal O from the internal bus master 4
Even if BA is output, the state of the output buffer 8 does not change, so no signal change occurs on the external bus 10. Therefore, unnecessary power consumption is avoided.

On the other hand, when the bus cycle is an access cycle to the external slave device 2, the source address signal AD
When the decoding result of D becomes ■H” and then the timing signal TS becomes ■H” and is activated,
The output of the AND gate 15 becomes ■H'', a trigger signal is input to the trigger terminal T of the output latch 10, the control signal from the internal bus master 4 is activated, and the output is sent from the output buffer 8 to the external slave device via the external bus 10. 2
is output to. In this embodiment, the access determination means is the address decoder 14, and the state change prohibition means is the AN.
Although the configuration is made up of the D gate 15 and the output latch 16, this configuration is merely an example, and it goes without saying that other configurations may be used.

0012

As explained above, according to the present invention, the access determination means determines whether the slave device accessed by the internal bus master is internal or external, and when the slave device accessed is internal, the internal bus master outputs an output signal. Since changes in the state of the signals that control the external slave devices that are accessed are prohibited, unnecessary signal changes on the external bus are eliminated when the internal slave devices are being accessed, and power consumption due to these signal changes is reduced. This has excellent effects such as reducing the power consumption of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration including a microcomputer according to the present invention.

FIG. 2 is a block diagram showing the configuration of an assertion prohibition section.

FIG. 3 is a timing chart showing changes in the state of each signal of the assertion prohibition section.

FIG. 4 is a block diagram showing a system configuration including a conventional microcomputer.

[Explanation of symbols]

1 Microcomputer 2 External slave device 4 Internal bus master 5 Internal slave device 10 External bus 13 Assertion prohibition section

Claims (1)

[Claims] 1. A microcomputer, which is connected to an external slave device via an external bus and includes an internal slave device, and a bus master that outputs a signal for controlling the internal slave device and the external slave device. access determination means for determining whether the access is to the external slave device or the internal slave device; and state change prohibition means for prohibiting a change in the state of a signal controlling the external slave device based on the determination result. A microcomputer characterized by comprising: