JP2007193431A - Bus controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus controller capable of preventing a through current from flowing, by controlling properly a bus floating preventive function, even when an operation frequency of a system is changed when a CPU accesses an external peripheral device via a bus, and capable of reducing electric power consumption. <P>SOLUTION: This bus controller is provided with a bus floating preventive function control timing setting part 9 for setting a timing setting value until operating the bus floating preventive function, in response to the operation frequency of the system, and a counter 10 for starting counting after reaching a bus floating condition, compares a timing set value 8 determined in response to the operation frequency of the selected system with a counter value 11 of the counter 10, and operates the bus floating preventive function, when the timing set value 8 gets equal to the counter value 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus control device that prevents a data bus signal terminal from being in a floating state when a CPU accesses an external peripheral device via a bus.

  Conventionally, when a CPU accesses an external peripheral device via a bus and the CPU and all the external peripheral devices connected to the CPU do not output data, the voltage is not completely turned off, but L and It is in an on state at an intermediate potential of H. For this reason, the data bus signal terminal is in a floating state, a through current flows, and there are problems such as an increase in power consumption, an increase in noise, and destruction of the device.

  In order to solve such a problem, a method using a bus hold circuit and means for avoiding a floating state of a bus by using a pull-up resistor and a pull-down resistor and preventing a through current from flowing are known.

Further, for example, in Patent Document 1, as a method for solving such a problem, when the floating state of the bus reaches a predetermined time set in advance, the terminal in the floating state is pulled up / down, or , L / H level output is performed to prevent the bus from floating.
JP 2003-150287 A

  However, in the conventional technique, in the method using the bus hold circuit, it is necessary to form a latch circuit for holding the potential immediately before the data bus signal terminal portion enters the floating state, which is often disadvantageous in terms of area.

  Further, when a pull-up resistor or a pull-down resistor is attached to the data bus signal terminal, a current flows through the pull-up resistor and the pull-down resistor except when the bus is floating, which is not desirable in terms of current consumption.

  Therefore, it is desirable to turn on the pull-up resistor and pull-down resistor or to output an L / H level signal only when the bus is in a floating state. Therefore, although there is a means for switching on / off of the pull-up resistor and the pull-down resistor by software control, it takes time and effort to control by software.

  Further, when the operating frequency of the semiconductor device including the CPU is changed according to the operating mode of the system, the bus interface timing is also changed according to the operating frequency, so that the bus floating state is prevented according to the timing. The function must be properly controlled.

  In view of such a situation, the present invention appropriately controls the bus floating prevention function even when the operating frequency of the system is changed when the CPU accesses the external peripheral device via the bus, thereby preventing the through current from flowing. An object of the present invention is to provide a bus control device that can prevent flow and reduce power consumption.

  In view of such a situation, the bus control device according to the first invention is a bus control device when the CPU accesses an external peripheral device via the bus, and starts counting after the bus access of the CPU is completed. And a control timing setting unit that determines a timing setting value for bus floating prevention function control by selecting from a control timing storage unit that stores the timing of bus floating prevention function control corresponding to operating frequencies of a plurality of systems, Control means for setting the data bus signal terminal to a predetermined potential based on the count value of the counter and the set value determined by the control timing setting unit is provided.

  The bus control device according to the second invention is characterized in that the control means sets the data bus signal terminal to a predetermined potential with a pull-down resistor.

  The bus control device according to a third invention is characterized in that the control means sets the data bus signal terminal to a predetermined potential with a pull-up resistor.

  The bus control device according to a fourth invention is characterized in that the control means puts the data bus signal terminal into an output mode and outputs an L level signal.

  The bus control device according to the fifth invention is characterized in that the control means puts the data bus signal terminal into an output mode and outputs an H level signal.

  The bus control device according to the sixth invention is characterized in that the bus floating prevention function control timing is output from the register to the control timing storage unit and can be changed according to the bus access timing of the external peripheral device. .

  According to the bus control device of the present invention, when the CPU accesses the external peripheral device via the bus, the bus control device of the present invention is used by having the bus floating prevention function control timing for each system operating frequency. Even if the operating frequency of the semiconductor device is changed during operation, the bus floating prevention function can be operated at an appropriate timing, preventing excessive through current from flowing, and reducing the power consumption of the semiconductor device. It can be reduced, and the excellent effect of being able to consider the environment can be achieved.

  Embodiments of a bus control device according to the present invention will be described below in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration of a semiconductor device having a bus control device according to the first embodiment of the present invention.

  In the embodiment shown in FIG. 1, an on / off pull-down resistor comprising an input buffer 1, an output buffer 2, a low-active output enable signal 3, a data bus signal terminal 4, a pull-down resistor 5, and a pull-down resistor control switch 6 is provided. It comprises an input / output buffer section and a bus floating prevention circuit section 7 for controlling the pull-down resistance control switch 6.

The bus floating prevention circuit unit 7 includes a bus floating prevention function control timing setting unit 9 that sets a timing setting value 8 until the bus floating prevention function is operated, a counter 10 that starts counting after entering the bus floating state, It comprises a comparator 12 that compares the timing set value 8 with the count value 11 of the counter 10.
The bus floating prevention function control timing setting unit 9 includes bus floating prevention function control timing storage units 13 and 14 that store the bus floating prevention function control timing according to the operating frequency of the system, and a selector 15.

  The bus floating prevention circuit unit 7 receives the operating frequency control signal 16 and determines the timing setting value 8 for controlling the bus floating preventing function by the selector 15 according to the operating frequency of the system, and enters the bus floating state. When the count value 11 of the counter 10 that started counting becomes equal to the control timing set value 8, the pull-down resistor control switch 6 is turned on, and the data bus signal terminal 4 is fixed to the L level by pull-down. Prevents the through current from flowing due to the bus floating state.

  Although FIG. 1 shows an input / output buffer with a pull-down resistor that can be turned on / off as an example, this may be an input / output buffer with a pull-up resistor that can be turned on / off.

  Further, FIG. 1 shows only two examples of the bus floating prevention function control timing storage unit. However, when there are three or more system operating frequencies, the bus floating prevention function control timing is determined according to the system operating frequency. It shall have a storage unit. Further, the bus floating prevention function control timing storage unit may be one, and a plurality of bus floating prevention function control timings may be stored in the storage unit.

  FIG. 2 is a timing chart showing how the bus floating prevention function control timing shown in FIG. 1 is selected corresponding to the operating frequency of the system.

  When the system operates at the clock frequency a, the bus floating prevention function control timing a is selected. When the system operates at the clock frequency b, the bus floating prevention function control timing b is selected.

  3 and 4 show timing charts when the CPU performs read access to the external peripheral device via the bus in the first embodiment of the present invention.

  Here, it is assumed that the clock frequency shown in the timing chart of FIG. 4 is ½ of the clock frequency shown in the timing chart of FIG. Also, the bus floating prevention function control timing shown in FIGS. 3 and 4 is 4 clocks after the end of bus access (when the clock frequency is a) and 2 clocks (when the clock frequency is b) as shown in FIG. ).

  As shown in FIG. 3, when operating at the clock frequency a, the bus floating prevention circuit unit 7 operates the bus floating prevention function 4 clocks after the bus access is completed, and turns on the pull-down resistance control switch 6. Thus, the data bus signal terminal 4 is fixed to the L level by the pull-down resistor 5.

  Next, when the system operation mode is changed and the system operating frequency is operating at the clock frequency b as shown in FIG. 4, the bus floating prevention circuit unit 7 prevents bus floating after two clocks after the bus access is completed. The data bus signal terminal 4 is fixed to L level by the pull-down resistor 5 by operating the function and turning on the pull-down resistor control switch 6.

  If there is no bus floating prevention function control timing for each system operating frequency, the same setting value will be used even if the system clock frequency is halved, and the bus floating prevention function is started. This doubles the amount of time until it passes, and an excessive through current flows.

  In addition, when changing the bus floating prevention function control timing by software control after changing the system operating frequency, there is an additional through current until the change of the bus floating prevention function control timing is reflected in addition to software control. It will flow.

  Therefore, by having the bus floating prevention function control timing according to the operating frequency of the system, even if the operating frequency of the system is changed depending on the operation mode, the bus floating preventing function can be appropriately controlled, and the through current due to the bus floating state is reduced. Can be prevented.

  In the description of the operation of the first embodiment of the present invention, the case where the CPU performs read access to the external peripheral device via the bus has been described as an example, but the same applies even when the CPU performs write access to the external peripheral device via the bus. In addition, the bus floating prevention function can be appropriately controlled according to the operating frequency of the system.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a semiconductor device having a bus control device according to the second embodiment of the present invention.

  In the embodiment shown in FIG. 6, an input buffer 19, an output buffer 20, an output enable signal 21 which is low active, an input / output buffer unit comprising a data bus signal terminal 22, and the data bus signal terminal 22 at the time of bus floating prevention function operation. It comprises selectors 23 and 24 for outputting a level, and a bus floating prevention circuit unit 25 for controlling the selectors 23 and 24.

The bus floating prevention circuit unit 25 includes a bus floating prevention function control timing setting unit 27 that sets a timing setting value 26 until the bus floating prevention function is operated, a counter 28 that starts counting after entering the bus floating state, The comparator 30 is configured to compare the timing set value 26 with the count value 29 of the counter 28.
The bus floating prevention function control timing setting unit 27 includes bus floating prevention function control timing storage units 31 and 32 and a selector 33 that store the bus floating prevention function control timing according to the operating frequency of the system.

  The bus floating prevention circuit unit 25 receives the operating frequency control signal 34, determines the timing setting value 26 for controlling the bus floating preventing function by the selector 33 according to the operating frequency of the system, and enters the bus floating state. When the count value 29 of the counter 28 that started counting becomes equal to the control timing set value 26, the L level output fixed selection signal 35 is controlled to output the L level to the data bus signal terminal 22, thereby Prevents through current from flowing due to the floating state.

  Although FIG. 6 shows a circuit that outputs L level when the bus is floating as an example, H level output may be performed when the bus is floating. FIG. 6 shows only two examples of the bus floating prevention function control timing storage unit. However, when there are three or more system operating frequencies, the bus floating prevention function control timing is determined according to the system operating frequency. It shall have a storage unit. Further, the bus floating prevention function control timing storage unit may be one, and a plurality of bus floating prevention function control timings may be stored in the storage unit.

  Also in the second embodiment of the present invention, a timing chart showing how the bus floating prevention function control timing shown in FIG. 6 is selected corresponding to the operating frequency of the system is shown in FIG. 2 as in the first embodiment. Can be represented. When the system operates at the clock frequency a, the bus floating prevention function control timing a is selected. When the system operates at the clock frequency b, the bus floating prevention function control timing b is selected.

  7 and 8 show timing charts when the CPU performs read access to the external peripheral device via the bus in the second embodiment of the present invention.

  Here, it is assumed that the clock frequency shown in the timing chart of FIG. 8 is ½ of the clock frequency shown in the timing chart of FIG. Also, the bus floating prevention function control timing shown in FIGS. 7 and 8 is 4 clocks after the bus access end (when the clock frequency is a) and 2 clocks (when the clock frequency is b) as shown in FIG. ).

  As shown in FIG. 7, when operating at the clock frequency a, after the bus access is completed, the bus floating prevention circuit unit 25 operates the bus floating prevention function after 4 clocks and sets the output enable signal 21 to the L level. The input / output buffer is set to the output mode, L is selected as the output data 36, and the L level is output from the data bus signal terminal 22.

  Next, when the system operating mode is changed and the system operating frequency is operating at the clock frequency b as shown in FIG. 8, the bus floating prevention circuit unit 25 prevents bus floating after two clocks after the bus access is completed. The function is operated, the output enable signal 21 is set to L level, the input / output buffer is set to the output mode, L is selected as the output data 36, and the L level is output from the data bus signal terminal 22.

  If there is no bus floating prevention function control timing for each system operating frequency, the same setting value will be used even if the system clock frequency is halved, and the bus floating prevention function is started. This doubles the amount of time until it passes, and an excessive through current flows.

  In addition, when changing the bus floating prevention function control timing by software control after changing the system operating frequency, there is an additional through current until the change of the bus floating prevention function control timing is reflected in addition to software control. It will flow.

  Therefore, by having the bus floating prevention function control timing according to the operating frequency of the system, even if the operating frequency of the system is changed depending on the operation mode, the bus floating preventing function can be appropriately controlled, and the through current due to the bus floating state is reduced. Can be prevented.

  In the description of the operation of the second embodiment of the present invention, the case where the CPU performs read access to the external peripheral device via the bus has been described as an example, but the same applies even when the CPU performs write access to the external peripheral device via the bus. In addition, the bus floating prevention function can be appropriately controlled according to the operating frequency of the system.

  When a memory is considered as an example of an external peripheral device, the period until the valid output data from the memory shifts to a high impedance state after the bus access is completed at the time of read access differs depending on the memory used. There are many cases. Therefore, it is necessary to set an appropriate bus floating prevention function control timing for each operating frequency of the system so that a bus conflict does not occur for an external peripheral device to be used.

  Furthermore, since external peripheral devices connected to a semiconductor device that integrates a CPU are often determined or changed after the semiconductor device is manufactured, the bus floating prevention function control timing can be changed by software. System design is possible.

When a hardware reset is applied after powering on the semiconductor device, the CPU initializes from an area (not shown) in which a memory fixed value (hereinafter referred to as “initial value”) is stored. A value is written to a register (not shown), and the initial value is loaded from the register to the bus floating prevention function control timing storage units 13, 14, 31, and 32. After that, when it is necessary to change the control timing of the bus floating prevention function due to a change in the external peripheral device connected to the semiconductor device, the bus floating prevention is performed according to the bus access timing of the changed external peripheral device. The function control timing is set. For example, when the bus control device reads data from the changed external peripheral device, depending on the timing at which the data bus is set to high impedance after the external peripheral device outputs valid data, etc. In the register, the timing value of the bus floating prevention function control is calculated and acquired by software, and the timing value is output from the register to the bus floating prevention function control timing storage unit 13, 14, 31, 32 and set. In addition to updating the value, the setting value in the initial value storage area of the memory is also updated. After the set value is updated, the bus is accessed from the CPU.
Alternatively, the timing value calculation itself may not be performed by software, and only the register setting change may be performed by software.

  With the above-described configuration, even when the external peripheral device connected to the semiconductor device is changed, it is possible to easily set the optimal bus floating prevention function control timing.

  The bus control device of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention.

It is the block diagram which showed an example of the structure of the semiconductor device which has a bus control apparatus in the 1st Embodiment of this invention. It is a figure which shows an example of the timing chart which shows the relationship between an operation clock frequency and a bus floating prevention function control timing about the bus control apparatus in the 1st and 2nd embodiment of this invention. FIG. 3 is a diagram illustrating an example of a timing chart at a clock frequency a when the CPU performs read access to an external peripheral device in the bus control device according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating an example of a timing chart at a clock frequency b when a CPU performs read access to an external peripheral device in the bus control device according to the first embodiment of the present invention. FIG. 9 is a diagram illustrating an example of bus floating prevention function control timing setting values in FIGS. 3, 4, 7, and 8. It is the block diagram which showed an example of the structure of the semiconductor device which has a bus control apparatus in the 2nd Embodiment of this invention. It is a figure which shows an example of the timing chart in the clock frequency a at the time of CPU read-accessing an external peripheral device about the bus control apparatus of the 2nd Embodiment of this invention. It is a figure which shows an example of the timing chart in the clock frequency b at the time of CPU read-accessing an external peripheral device about the bus control apparatus of the 2nd Embodiment of this invention.

Explanation of symbols

1, 19 Input buffer 2, 20 Output buffer 3, 21, 38 Output enable signal 4, 22 Data bus signal terminal 5 Pull-down resistor 6 Pull-down resistor control switch 7, 25 Bus floating prevention circuit unit 8, 26 Bus floating prevention function control timing Set value 9, 27 Bus floating prevention function control timing setting unit 10, 28 Counter 11, 29 Count value 12, 30 Comparator 13, 14, 31, 32 Bus floating prevention function control timing storage unit 15, 23, 24, 33 Selector 16, 34 Operating frequency control signal 17, 37 Input data 18, 36, 39 Output data 35 L level output fixed selection signal

Claims (6)

A bus control device used when a CPU accesses an external peripheral device via a bus,
A counter that starts counting after the end of bus access of the CPU;
A control timing setting unit that selects a timing setting value for bus floating prevention function control by selecting from a control timing storage unit that stores the timing of bus floating prevention function control corresponding to the operating frequency of a plurality of systems;
Control means for setting the data bus signal terminal to a predetermined potential from the count value of the counter and the set value determined by the control timing setting unit;
A bus control device comprising:   2. The bus control apparatus according to claim 1, wherein the control means sets the data bus signal terminal to a predetermined potential by a pull-down resistor.   3. The bus control device according to claim 2, wherein the control means sets the data bus signal terminal to a predetermined potential with a pull-up resistor.   2. The bus control device according to claim 1, wherein the control means sets the data bus signal terminal to an output mode and outputs an L level signal.   2. The bus control device according to claim 1, wherein the control means sets the data bus signal terminal to an output mode and outputs an H level signal.   6. The bus floating prevention function control timing is output from a register to the control timing storage unit and can be changed according to a bus access timing of an external peripheral device. Bus control device.

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