JPH02284245A - Cache memory control system - Google Patents

Abstract

PURPOSE:To remove restrictions in the use of software and the configuration of system by setting an address area of which a buffer memory need not be referred to by the software. CONSTITUTION:An address setting register 3 holds information related to the address area for which the buffer memory 6 need not be referred to by access from a processor. At the time of memory access from the processor, it is checked whether its access address is included in the address area specified by the information of the address setting register 3 or not by a decision circuit 4. If it is decided to be included in the address area as a result, its memory access is controlled so as to access a main storage part 7 always without referring to the buffer memory 6 at all by a memory access control circuit 5. Thus, the configuration of the system and the use of the software are never given any restriction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method for a system using a memory and a processor, and more particularly to a control method when a processor accesses memory.

[Conventional technology]

Conventionally, in this type of cache memory control system, a hardware address decoder determines an address area that does not refer to the buffer memory.

[Problem to be solved by the invention]

The conventional cache memory control method described above has a drawback in that the address area settings are uniformly determined because of the hardware configuration. Therefore, when constructing a cache memory system, the specifications of the software that runs on it must be considered, and there are also limitations on the software that is used.

An object of the present invention is to eliminate these drawbacks and provide a cache memory control method that eliminates restrictions on software use and system configuration by setting an address area that does not refer to buffer memory by software. .

[Means to solve the problem]

The configuration of the present invention includes a high-speed buffer memory between a processor and a main memory, and when the corresponding data on the main memory has been copied to the buffer memory when the processor accesses the memory, the buffer In a cache memory control method, the cache memory control method performs control such that when the memory is not being copied, the main memory is directly accessed and a data area specified by the access address is copied into the buffer memory,
A register is provided for setting a predetermined address area, and when there is an access from the processor within the predetermined address area, the main memory is always accessed without referring to the buffer memory. Features.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the internal configuration of an embodiment of the present invention. The system of this embodiment has a buffer memory 6 between a processor (not shown) and a main memory section 7, and these main memory section 7 and buffer memory 6 are connected to an address bus 1.
A memory access control unit 5 accessed by an address from is controlled by signals from an address setting register 3 and a determination circuit 4. In this embodiment, the address setting register 3 holds information regarding address areas that do not refer to the buffer memory 6 when accessed by the processor. When the processor accesses the memory, the judgment circuit 4 determines whether the access address 1 falls within the address area specified by the information in the address setting register 3.
will be checked. As a result, if it is determined that the memory is within the address area, the memory access is controlled by the memory access control circuit 5 to always access the main memory 7 without referring to the buffer memory 6, and If it is determined that it does not fit in the normal buffer memory 6
Control using

〔Effect of the invention〕

As explained above, the present invention has the advantage that by setting an address area that does not refer to a buffer or memory in software, there is no restriction on the system configuration or use of software. Furthermore, since the area designation can be dynamically changed even while the system is in operation, the efficiency of the entire system can be improved.

Memory department.

Claims (1)

[Claims] A high-speed buffer memory is provided between the processor and the main memory, and when the corresponding data on the main memory has been copied to the buffer memory when the processor accesses the memory, the buffer memory is accessed and copied. A register for setting a predetermined address area in a cache memory control method that directly accesses the main memory and controls to copy a data area specified by the access address into the buffer memory when the access address is not specified. 1. A cache memory control method, characterized in that when there is an access from the processor within the predetermined address area, the main storage section is always accessed without referring to the buffer memory.