JPH03156653A - Cache memory control system - Google Patents

Abstract

PURPOSE:To minimize the influence of the individual locality of software to be actuated to the cache hit rate by offering the set number of tag memories suited to each software to be actuated to a cache memory controller. CONSTITUTION:When an optional software is set on the hardware resources for the first time, a CPU 2 tries all set numbers of available tag memories in a current CPU system under the control of a cache controller 1. A counter means 3 counts the hit frequency of each case, and this count value data 12 is supplied to the CPU 2. The CPU 2 compares these count values with each other, and the set number selection data 13 having the largest count value is supplied to the controller 1. Hereafter the CPU 2 actuates the controller 1 with the set number of tag memories suited to the relevant software at actuation of the software. As a result, the influence of the software locality is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method, and more particularly to a control method for selecting the number of sets of tag memories in a cache memory system with a fixed cache memory capacity.

[Conventional technology]

Conventionally, this type of cache memory control method has been performed based on the general locality of software only at the design stage of the CPU system.

[Problem to be solved by the invention]

In the conventional cache memory control method described above, the number of tag memory sets is determined only at the design stage of the CPU system.
Since the number of tag memory sets is determined based on the general locality of software, it is rare to be able to set the number of tag memory sets appropriate for the locality of each piece of software actually used in the CPU system. The object of the present invention is to solve this problem by determining the locality of each piece of software and obtaining the number of tag memory sets suitable for that software. The object of the present invention is to provide a cache memory control method that achieves the following.

[Means to solve the problem]

The configuration of the present invention is such that in a cache memory control method of a system in which a CPU and a cache memory controller that can arbitrarily set the number of tag memories set are connected via an address line, an access address of the CPU is used to hit the cache memory. It has a counting means for counting signals indicating that the tag memory has been set or mishit, and supplies the count value obtained by the counting means to the CPU as one factor for determining the number of sets of the tag memory.
Accordingly, the number of tag memory sets suitable for each arbitrary software is set.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. This embodiment is composed of a cache memory controller 1, a CPU 2, and a counting means 3.

The cache memory controller 1 has a built-in tag memory, and is a write-through type in which the number of tag memory sets can be arbitrarily set.
When access is started, the cache memory controller 1 outputs a hit signal 11 to the CPU 2 if the data desired by the CPU 2 exists in the cache memory. The counting means 3 counts the hit signal 11 output from the cache memory controller 1, and can also be read from the CPU 2.

Therefore, when arbitrary software is installed on the above-mentioned hardware resources for the first time, the CPU 2 controls the cache memory controller 1 to try all the tag memory sets that can be achieved with the current CPU system. The number of hits in each case is counted by the counting means 3, the counted value data 12 is supplied to the CPU 2, the counted values are compared in size, and the set number selection data 13 of the largest counted value is obtained. Retains and cache memory
Supplied to controller 1.

From next time onwards, when this software runs, the CPU
At step 2, the cache memory controller 1 is controlled to operate with the set number of tag memories suitable for the software.

FIG. 2 is a block diagram of a second embodiment of the invention.

The cache memory controller 1' of this embodiment is the first cache memory controller 1'.
In addition to the functions of the cache memory controller 1 of the embodiment described above, the cache memory controller 1 has a function of outputting a signal 14 indicating that a replacement has occurred. The counting means 3 counts this replacement generation signal 14.

In this embodiment, since the signal 14 indicating that a replacement has occurred is counted by the counting means 3, there is no need to count the write access of the CPU 2, which does not need to be counted in a write-through type cache memory controller.
There is an advantage that the count value becomes a more effective factor in determining the number of tag memory sets, and a more suitable number of tag memory sets can be calculated.

〔Effect of the invention〕

As explained above, the present invention provides the cache memory controller with the number of tag memory sets suitable for each piece of software to be run, thereby minimizing the effect of the locality of each piece of software to be run on the cache hit rate. be.

[Brief explanation of the drawing]

1 and 2 are block diagrams of first and second embodiments of the present invention. 1.1'...cache memory controller, 2
... CPtJ, 3... Counting means, 10... Address, 11... Hit signal, 12... Data, 13...
...Set number selection signal, 14...Replace generation signal.

Claims (1)

[Claims] In a cache memory control method of a system in which a CPU and a cache memory controller that can arbitrarily set the number of tag memory sets are connected via an address line, an access address of the CPU hits or misses the cache memory. The count value obtained by the counting means is supplied to the CPU as one factor for determining the number of sets of the tag memory, and the CPU is used to control each arbitrary software. A cache memory control method characterized by setting an appropriate number of tag memory sets.