JPH0784873A - Storage device - Google Patents

Abstract

PURPOSE:To eliminate the concentration of access on a specific bank even when the amount of data is small and to prevent only memory elements of a bank from concentrically get out of order by making respective banks uniform in use frequency as to a bank type storage device. CONSTITUTION:Counters 3a-3d provided corresponding to respective bands count the frequencies of data writing to banks 2a-2d and a bank determination part 4 selects the bank having the least number of written data by referring to the counted values of the counters 3a-3d, and writes new data in the selected bank.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device for storing data in a bank system.

[0002]

2. Description of the Related Art A memory address space that can be handled by a CPU is fixed for each CPU, but a bank system has been conventionally used when it is desired to use a main memory having a larger capacity than this memory address space. This bank system is
Prepare a main memory device with a capacity larger than the memory address space, divide the memory area of this main memory device into a plurality of banks so that the memory capacity of one bank is equal to the memory address space, and access in bank units at the time of access. , It intends to use a large storage capacity by switching the bank to be accessed.

In the conventional bank type storage device, when storing data, first, the data is stored in a certain bank, and when the bank becomes full, the bank is switched and stored in the next bank. It was a thing.

[0004]

In the conventional bank type storage device described above, when one bank is full, the next bank is used. Therefore, when the data amount is small, one specific bank is used. Access was concentrated on. Therefore, there has been a problem that only the memory elements in the bank where the access is concentrated fail intensively.

The present invention has been made in view of the above points, and in a bank type storage device, the use frequency of each bank is equalized, and access is concentrated on a specific bank even when the amount of data is small. The purpose is to prevent intensive failure of only the memory elements in that bank.

[0006]

In order to achieve the above object, the present invention provides a storage section divided into a plurality of banks, a plurality of counters for counting the number of times data is written to each of the banks, and The memory device is configured by a control unit that refers to the count numbers of the plurality of counters at the time of writing data to the storage unit and controls so as to write the data to the bank having the smallest number of writes.

[0007]

According to the present invention, with the above configuration, the number of times of writing data for each bank is counted by the counter provided corresponding to each bank, and the number of data already written by the control unit is the smallest based on the count number of the counter. A bank is selected and control is performed so that new data is written in the selected bank.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a storage device according to the present invention.

Reference numeral 1 denotes a storage device, which is a bank 2a to 2
A storage unit 2 including d, counters 3a to 3d, a bank determining unit 4 as a control unit, and a bank managing unit 5. The storage device 1 includes a control line and a data line for the CPU 6
When a write instruction is issued from the CPU 6 via the control line, the CPU 6 receives the data to be written via the data line from the CPU 6 and writes the data in the storage unit 2.
When there is a read instruction from the control line, the data is read from the storage unit 2 and output to the CPU 6 via the data line.

As a write instruction from the CPU 6, the write enable signal becomes HIGH which means "true",
When this write enable signal is HIGH, it is an address that identifies a bank and an address in that bank, and is a software address that is the address of the data to be written in the software operating in the CPU 6, and the amount of data to be written. That is, the number of bytes is the storage device 1
Is output to the bank management unit 5.

On the other hand, as a read instruction from the CPU 6, the read enable signal is "HIGH" which means "true".
When the read enable signal is HIGH, the soft address of the data to be read and the data amount of the data to be read, that is, the number of bytes are output to the bank management unit 5 of the storage device 1.

In this embodiment, as shown in FIG. 1, the storage unit 2 is divided into four banks 2a to 2d, and counters 3a to 3d are provided for each of the banks 2a to 2d. The counters 3a to 3d count the number of times the write enable signal for the corresponding banks 2a to 2d becomes HIGH, and the count number can be referred to by the bank determining unit 4. Also, the bank determination unit 4
Holds the address in the bank of the head portion of the empty memory of the banks 2a to 2d.

Next, the operation of the storage device 1 according to the present invention will be described.

First, the write operation to the storage device 1 will be described.

The bank management unit 5, which has received the write instruction from the CPU 6 via the control line, uses the soft address of the data to be written received from the CPU 6 as the banks 2a to 2d based on the internal address-bank conversion table. Of the specified bank number, the write enable signal to the bank determination unit 4 is set to HIGH, and the calculated bank number, the soft address of the data to be written, and the data amount of the data to be written are set to the bank determination unit. Output to 4. The address-bank conversion table holds the soft address of the data to be written and the bank number of the bank storing the data in association with each other, and can be updated by an instruction from the bank determination unit 4. Here, the bank number of the bank 2a is 1
It is assumed that the bank number of the bank 2b is 20, the bank number of the bank 2c is 30, the bank number of the bank 2d is 40, and the bank number 10 of the bank 2a is obtained based on the address-bank conversion table.

The bank determination unit 4 which detects that the write enable signal from the bank management unit 5 has become HIGH
Refers to the respective count numbers of the counters 3a to 3d and selects the counter with the smallest count number. Here, it is assumed that the count number of the counter 3c is the smallest. Then, it is checked whether or not the bank number of the bank for the selected counter is equal to the bank number from the bank management unit 5, and only when they are not equal, the bank number of the bank for the selected counter is set in the bank management unit 5. Output. Here, since the bank number of the bank 2c for the selected counter 3c is 30, and the bank number from the bank management unit 5 is 10, they are not equal, so the bank number 30 is output to the bank management unit 5.

The bank management unit 5, which has received the bank number 30 from the bank determination unit 4, rewrites the address-bank conversion table so that the bank number 30 of the bank 2c for the counter 3c selected by the bank determination unit 4 and the above-mentioned software. It is associated with the address.

On the other hand, the bank determining section 4 refers to the address in the bank of the head portion of the empty memory of the banks 2a to 2d which is held in advance, and starts from the head portion of the empty memory of the bank 2c for the selected counter 3c. Counter 3c and bank 2c selected to write data
The write enable signal for is set HIGH, and the data amount of the data to be written received from the bank management unit 5 is output to the bank 2c. Further, the bank determination unit 4 holds the address in the bank in which the data is written and the soft address of the data to be written received from the bank management unit 5 in association with each other, and further, the write received from the bank management unit 5. The address in the bank of the head portion of the empty memory of the bank 2c is shifted by the amount of data to be inserted.

The counter 3c which has detected that the write enable signal from the bank determining section 4 has become HIGH is
Count up by one. Further, the bank 2c that has detected that the write enable signal from the bank determination unit 4 has become HIGH acquires the data to be written from the CPU 6 via the data line, and receives the data from the bank determination unit 4. Only the amount of data to be written is written from the head portion of the empty memory of the bank 2c.

Next, the read operation from the storage device 1 will be described.

The bank management unit 5, which has received a read instruction from the CPU 6 via the control line, uses the soft addresses of the data to be read received from the CPU 6 as the banks 2a to 2d based on the internal address-bank conversion table. Of the specified bank number, the read enable signal to the bank determination unit 4 is set to HIGH, and the calculated bank number, the soft address of the data to be read, and the data amount of the data to be read are set to the bank determination unit. Output to 4. Here, the bank number 30 of the bank 2c is based on the address-bank conversion table.
Is obtained.

The bank determination unit 4 which detects that the read enable signal from the bank management unit 5 has become HIGH
Refers to the correspondence between the soft address of the written data held at the time of writing the data and the address of the data in the bank, and the data is read from the soft address of the data to be read received from the bank management unit 5. Find the address in the stored bank. Further, the read enable signal for the bank having the bank number received from the bank management unit 5, that is, the bank 2c is set to HIGH, and the address in the bank of the data to be read obtained here and the address received from the bank management unit 5 are received. The amount of data to be read and the amount of data to be read are output to the bank 2c.

The bank 2c, which has detected that the read enable signal from the bank determination unit 4 has become HIGH, receives from the bank management unit 5 from the address in the bank of the data to be read received from the bank determination unit 4. The data is read by the amount of the data to be read, and the read data is output to the CPU 6 via the data line.

[0025]

As described above, according to the present invention,
Each bank has a counter, counts the number of times data is written to each bank, and refers to the count number of the counter when writing the next data, and manages the bank so that the bank with the smallest number of writes is written. Therefore, even if the amount of data is small, access does not concentrate on a specific bank, the frequency of use of memory elements in each bank can be equalized, and only the memory elements in a specific bank fail intensively. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of a storage device according to the present invention.

[Explanation of symbols]

 1 Storage Device 2 Storage Units 2a, 2b, 2c, 2d Banks 3a, 3b, 3c, 3d Counter 4 Bank Determination Unit 5 Bank Management Unit 6 CPU

Claims (2)

[Claims] 1. A storage unit divided into a plurality of banks, a plurality of counters for counting the number of times of writing data to each of the banks, and a count number of the plurality of counters when writing data to the storage unit. And a control unit that controls so that data is written in a bank that has the least number of times of writing. 2. The count of the number of times of data writing is
The storage device according to claim 1, wherein the storage device counts rising edges of the write enable signal.