JPH03147157A - Information processor - Google Patents

Abstract

PURPOSE:To suppress the number of times for generating the interruption of a page fault at a minimum by pulling a page, which is most frequently accessed, onto a main storage by using an interruption generating circuit using a timer circuit. CONSTITUTION:A comparator circuit 4 stores the page ID of the page, for which the number of times for access is smallest out of the pages existent in a main storage 1, into an area 20 and stores the page ID of the page, for which the number of times for access is largest, into an area 21. The comparator circuit 4 compares the number of times for access of the areas 20 and 21 further and in the case of (the contents of 20) < (the contents of 21), a trigger request is outputted to a trigger generating circuit 6. Then, the trigger generating circuit 6 outputs a count instruction to a timer circuit 8. When there is no new trigger request during the count of the timer and specified time is counted, the timer circuit 8 outputs an interruption request to a controller 11. Thus, the number of times for generating the interruption of the page fault are suppressed at a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an information processing device designed to effectively utilize a main storage device in a virtual storage system.

[Conventional technology]

Conventionally, in information processing devices that employ this type of virtual storage method, when a central processing unit (hereinafter referred to as CPU) accesses a logical address space, a page fault occurs if the logical address does not exist in main memory. When an interrupt occurs, the least frequently accessed page on the main memory is pushed to one storage device, and the desired page is imported from the external storage device into the main storage device.

[Problem to be solved by the invention]

In the conventional technology described above, when a page access request that is not in main memory occurs, such as when a task changes, the least frequently accessed page in main memory is evicted by a page fault interrupt, but that page is moved to the next page. Although it exists in main memory until the page fault interrupt that occurs in The drawback was that the equipment was not utilized effectively.

[Means to solve the problem]

The information processing device of the present invention includes a comparison circuit for comparing and calculating the number of page accesses in management information of pages in a main storage device and selecting the most frequently accessed page; and receiving an output from the comparison circuit; A trigger generation circuit that generates a hardware trigger from the output, and a trigger generation circuit that receives the trigger from the trigger generation circuit, counts a predetermined number of times, outputs a strobe signal at the end of the count, and outputs a strobe signal during the count. It has a timer circuit that starts counting again from the initial setting value when a trigger from the generation circuit occurs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, l is the main memory, 2 is a page access management table, 3 is a data bus, 4 is a comparison circuit for comparing and calculating the number of accesses for the least number of pages, and 5 is the comparison circuit 4 for calculating the number of accesses for the least number of pages. 6 is a trigger generation circuit which receives the output from the comparator circuit 4 and outputs a hardware trigger (Hars); 7 is an output signal which outputs an output pulse from the trigger generation circuit 6;

8 is a timer circuit for making an interrupt request to the next-stage interrupt controller after receiving the trigger output pulse for a certain period of time, 9 is an external storage device, and 10 is a timer circuit for sending an interrupt request from the timer circuit 8 to the interrupt controller described later. 11 is an interrupt controller that arbitrates for interrupt requests from other Ilo etc. in addition to the timer circuit 80 interrupt requests, and outputs interrupt requests to the CPU; 12 is an interrupt controller for signals other than the timer circuit 8; Interrupt request signals from other machines/○, machine 3 represent output signals from the interrupt controller for transmitting one of the many interrupt requests from 10 and 12 to the CPU, and 14 represent the CPU.

FIG. 2 shows the details of the page management table shown in FIG. 1. When the main memory is divided into certain areas, each area is called a page, and the page ID 15 is attached to each 4. 16 is an access count area indicating how many times each page has been accessed, and 17 is a control bit other than 15.16.

Figure 3 shows how the page management table is updated when an access actually occurs to a logical address, from Figure 3(a) to Figure 3(b), and then to Figure 3(b).
Updated to the state shown in figure (c)<(when n=10)
.

In Fig. 3, both 18 and 19 are page tables located on the main memory, but 18 represents those with pages on the main memory that have ■ to ■ for explanation purposes, and 19 represents those that have pages on the external storage. For the purpose of explanation, it means that those with pages have ■ ~ 0, and 20 is the page ID that has been accessed the least number of times among the pages existing in the main memory among the 18 ■ ~ ■.
21 represents the area for managing the page ID that has been accessed the most among the pages existing in the external storage device from ■ to 0, and 2
2 to 24 and 25 to 27 represent the updating process, which will be explained in "Operation" below.

Next, the operation will be explained. When the CPU 14 accesses the main memory device 1 or the external memory device 9, the comparison circuit 4 in FIG.
It is stored in area 20 in the figure, and the page ID of the page that has been accessed the most among pages not present in the main memory is stored in area 21 in FIG.

Comparison circuit 4 further compares the number of 7 accesses of 20 and 21, and if (contents of 20) < (contents of 21), outputs a trigger request to trigger generation circuit 6. . The trigger generation circuit 6 is a timer circuit 8.
Outputs count instructions for. Furthermore, when there is no new trigger request during timer counting and the specified time has been counted, the timer circuit 8 outputs an interrupt request to the interrupt controller 11. And interrupt controller 1
1 outputs a page update interrupt request to the CPU 14, and the CPU 14 executes interrupt processing from there.

Figure 3 shows how the page is updated after an interrupt occurs, and the occurrence of an interrupt means (contents of 20)
Since <(contents of 21), first, since the number of accesses of 21 is the maximum, and the number of accesses of 21 is the minimum, the contents of each are swapped. At this time, the content of ■ has been accessed once, so the number of accesses has been increased to 26.
(251 times) (see steps 22 to 24). At the same time, the contents of 20.21 were also updated at this time, and each
, becomes 0 (Fig. 3(b)).

Using the same idea, ■ and 0 are swapped in FIG. 3(b) (the state after the swap is shown in FIG. 3(C)).

In this state, (contents of 20) > (contents of 21), so no further interruptions will be made until an access to the external memory page occurs and (contents of 20) < (contents of 21). Does not occur.

It is assumed that the above-mentioned interrupt processing utilizes the time when the data bus of the CPU is idle to reduce the time required for the main interrupt processing.

In this way, the most frequently accessed pages can be
Using an interrupt generation circuit that uses a timer circuit, the number of page fault interrupts generated can be reduced by using bus idle time to retrieve pages needed for the next task at the time of a task change, etc., into the main memory. to a minimum,
The through-foot of the system can be improved.

〔Effect of the invention〕

As explained above, the present invention uses an interrupt generation circuit using a timer circuit to select pages that are accessed most frequently, and to select pages that will be needed for the next task at the time of a task change, etc. by checking the available bus time, etc. By using the data and pulling it into the main memory, the number of page fault interrupts can be minimized and system throughput can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of a page access management table, and FIG. 3 is a diagram showing how a page is updated. 1...Main storage device, 2...Page access management table, 3...Data bus, 4...
... Comparison circuit, 5 ... Output signal from the comparison circuit, 6 ... Trigger generation circuit, 7 ...
Output signal from trigger generation circuit, 8... Timer circuit, 9... External storage device, 10... Interrupt request signal, 11... Interrupt controller 12. ...Interrupt request signal, 13...
Output signal from interrupt controller, 14...
CPU, 15...Page ID, 16...
・Access count area, 17...Other control bits, 18゜19...Specific diagram of page management table, 20...Area representing the least accessed page ID , 21... Area representing the most accessed page ID, 22 to 24.2
5-27...Arrow for updating.

Claims (1)

[Scope of Claims] A comparison circuit for comparing and calculating the number of page accesses in management information of pages in a main storage device and selecting the most frequently accessed page; and a comparison circuit for receiving an output from the comparison circuit; A trigger generation circuit that generates a hardware trigger; and a trigger generation circuit that receives the trigger from the trigger generation circuit, counts a predetermined number of times, outputs a strobe signal when the count ends, and outputs a strobe signal during the count. 1. An information processing device comprising: a timer circuit that restarts counting from an initial setting value when a trigger occurs.