JPH07121431A - Address controller - Google Patents

Abstract

PURPOSE:To use a storage space as a plural ring buffers with variable capacity. CONSTITUTION:Address designation means 33-36 designating addresses for accessing to a storage means for the respective access types of plural devices, a storage means 31 storing information showing the boundary address of divided areas and an address control means 32 monitoring in which area the address that the address designation means designates exists based on the address which the address designation means designates and the boundary address which information stored in the storage means shows and controlling the address designation means so that a next address is set to be a head address when the address becomes equal to the end address of one of the areas are provided. Thus, the storage space can be used as a plural ring buffers with variable capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address control device, and more particularly, it has a storage means accessed by a plurality of devices for writing and reading data, and divides the storage space of the storage means into a plurality of areas. The present invention relates to an address control device for controlling an address for accessing the storage means of the plurality of devices in an image processing device to be used.

[0002]

2. Description of the Related Art Conventionally, in an image processing apparatus, a plurality of devices such as image input means and image processing means and storage means such as memory are connected to an internal data bus, and images are transferred between the devices via the bus and storage means. Exchanging data. At this time, the storage space of the storage means is divided into a plurality of areas in advance and assigned as an input area or an output area of each device.

By the way, the size of an image read from the outside is not always constant, for example, as when a manuscript of various sizes is read and copied in a copying machine. Therefore, it is necessary to change the size of each divided area of the storage space according to the size of the image. A method for changing the size of each divided area of the storage space is disclosed in, for example, Japanese Patent Laid-Open No.
There is a technology disclosed in Japanese Patent Application Laid-Open No. 297935, which is a storage means based on an address obtained by calculation by a value of a partition register holding a value indicating each area of a storage space and a value of an address counter. By accessing, the size and position of each area can be changed according to the content of the calculation.

[0004]

However, in the above technique, the size and position of each region of the storage space can be made variable, but the image itself of the image itself has become higher due to the recent improvement in the image quality and full colorization. To handle the increase in data volume,
The total storage capacity itself must be increased, which leads to an increase in cost and an increase in the amount of hardware.

As a method for coping with an increase in the amount of data without increasing the storage capacity itself, there is a method in which each area is used as a ring buffer. In the above technique, the address from the external device is monitored and the calculation by the external device is performed. Since there is no means for implementing a ring buffer without the need to change the contents or the contents of the address counter, the address control device according to this technique needs to constantly monitor the address by an external device, and the area where the address is located. When it becomes equal to the end address of, the contents of the address counter or the contents of calculation must be changed by the external device. Therefore, the efficiency of the device controlling the address control device according to this technique is reduced.

An object of the present invention is to solve the above-mentioned problems, and an object thereof is to provide an address control device which can use a storage space as a plurality of variable capacity ring buffers.

[0007]

In order to solve the above-mentioned problems, the present invention has a storage means accessed by a plurality of devices for writing and reading data, and the storage space of the storage means has a plurality of areas. In an image processing apparatus that is used by dividing into a plurality of devices, an address specifying unit that specifies an address for accessing the storage unit for each access type of the plurality of devices, and a boundary address between the divided regions. Storing means for storing information indicating
Based on the address designated by the address designating means and the boundary address indicated by the information stored in the storing means, it is monitored in which area the address designated by the address designating means is located. When it becomes equal to the end address of that area, the address control means for controlling the address specifying means is set so that the next address becomes the start address of the area.

Further, the address control means controls the address designating means such that when the address designated by the address designating means becomes equal to the end address of any area, the next address is set as the leading address of the area. At this time, the head address is obtained by calculation from the boundary address between the areas indicated by the information stored in the storage means.

[0009]

Since the address control device of the present invention is provided with the address designating means, the storing means and the address controlling means as described above, the storage space can be used as a plurality of variable capacity ring buffer areas. Further, since it is provided with a means for monitoring in which area the address designated by the address designating means is present and setting the next address as the start address of the area when the address becomes equal to the end address of any area, There is no need for external control.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining one embodiment of an address control device according to the present invention, and FIG. 2 is a diagram showing an example of a divided storage space of a storage means. In FIG. 1, the image input means 11 is for taking in image data from the outside, and the image processing means 12 is for performing various image processing such as compression, decompression, and editing on the image taken in by the image input means 11. The storage means 14 is accessed by each means connected to the image data bus for writing and reading the image data, and the image output means 15 outputs the image data to the outside. The address control means 16 controls an address for accessing the storage means 14 of each means connected to the image data bus, and the control means 13 controls the operation of each means through the control bus. It is a thing. If the image processing apparatus is, for example, a copying machine, the image input means 11
Is a scanner mechanism for converting an image recorded on a recording medium such as paper into a digital signal, and the image output means 15
Is a print mechanism for recording an image signal on a recording medium such as paper.

In the above image processing apparatus, the storage means 1
The storage space 4 is used by being divided into a plurality of areas as shown in FIG. 2, for example. 2 shows the image input means 11
The image read from the outside by the image processing means 12
As the storage area of the image data processed by the image output means 15 to the outside, the area of the image data output from the image input means 11 and input to the image processing means 12 is sequentially set as the storage area from the front side. 1 shows the storage space when the area of the image data output from the image processing means 12 and input to the image output means 15 is assigned to the area 2. The writing and reading of each means are controlled by the write address and the read address of the means, and the address itself is controlled by the address control means 16. As described above, FIG. 1 shows an example of the configuration of an image processing apparatus having a storage unit that a plurality of devices access for writing and reading data, and the storage space of the storage unit is divided into a plurality of areas for use. Is shown.

FIG. 3 is a diagram showing an embodiment of the address control device of the present invention when the storage space is used as illustrated in FIG. 2, 31 is a register, 32 is an address controller, and 33 to 36. Indicates an address counter. In FIG. 3, the register 31 stores information indicating the boundary address of the two areas in the storage space shown in FIG.
The address counter 33 controls the output of the image input unit 11, the address counter 34 controls the input of the image processing unit 12, and the address counter 3.
Reference numeral 5 designates an address for controlling the output of the image processing means 12, and the address counter 36 designates an address for controlling the input of the image output means 15. The address controller 32 monitors the address designated by the address counters 33 to 36 based on the values of the signals AD1 to AD4 and the signal RD, and when the address becomes equal to the end address of either of the two areas, the signals CD1 to CD1 are output. The head address of the area is set in the corresponding address counter by the CD4 and the signals CNT1 to CNT4 at the same timing as the increment of the address counter.

The signal LD is data for setting data in the register 31 and the address counters 33 to 36. The signal LER is a load enable signal for setting data in the register 31. Signal LE1
~ LE4 are load enable signals for setting data in the address counters 33 to 36, respectively. The signals ET1 to ET4 are sent to the address counter 33 to respectively.
36 count enable signal. Signals AD1 to A
D4 is output data of the address counters 33 to 36, respectively. The signal RD is output data of the register 31. The signals CD1 to CD4 are output data of the address controller 32 for setting the start address of the area including the address designated by the corresponding address counter in the address counter 32. The signals CNT1 to CNT4 are control signals of the address controller 32 for setting the start address of the area including the address designated by the corresponding address counter in the address counter 32. The values of the four address counters are addresses in the storage space of the storage means 14. One of the values is selected by a selector (not shown) and output to the storage unit 14. Hereinafter, assuming that the boundary address is the start address and end address of the area 1 and the end address of the area 2, the operation of the embodiment of the present invention will be described.

First, the control means 13 causes the load enable signal LER and the load enable signals LE1 to LE1.
LE4 is sequentially issued, information indicating the start address and end address of area 1 and the end address of area 2 is set in register 31, the start address of area 1 is set in address counter 33 and address counter 34, and address counter 35 is set. And the start address of the area 2 is set in the address counter 36. After the completion of the above-mentioned initialization, the image input means 11, the image processing means 12, and the image output means 15 start their respective operations, and the respective means operate as the storage means 14.
To the count enable signals ET1 to ET each time a predetermined amount of data is accessed for writing or reading.
4 is issued and the value of the corresponding address counter is incremented. For example, an address is assigned for each byte in the storage space, and the image input means 11
When 8 bytes of data are written in the storage means 14, the address counter 33 has a value obtained by adding 8 to the value before writing.

When the value of any of the address counters 33 to 36 becomes equal to the end address of either of the two areas, the address controller 32 sets the start address of the area to the address counter which becomes equal to the end address. Set at the same timing as the increment of. For example, when the value of the address counter 33 becomes equal to the end address of the area 1, the address controller 32 issues the control signal CNT1 and outputs the head address of the area 1 to the data bus CD1 to output the address 1 of the area 1 to the address counter 33. Set the start address. The above-mentioned setting of the head address is the same for other address counters. If the value of a certain address counter is an address in the area 2, if the value of the address counter becomes equal to the end address of the area 2, the address counter is set. Is set to the start address of the area 2. Although the register 31 does not store the information indicating the start address of the area 2, the start address of the area 2 can be obtained by calculation from the end address of the area 1. For example, if an address is assigned for each byte in the storage space and there is an area of n bytes (n is an integer of 0 or more) between area 1 and area 2, the start address of area 2 is area 1 It is a value obtained by adding n + 1 to the end address of. As described above, the areas 1 and 2 can be used as ring buffers.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the configuration of the image processing apparatus is not limited to the configuration illustrated in FIG. 1, and a plurality of devices have a storage unit that is accessed for writing and reading data, and the storage space of the storage unit is divided into a plurality of areas. Any configuration may be used as long as it is an image processing apparatus to be used. Further, it is apparent that the division mode of the storage space and the allocation of the divided areas are not limited to the division mode and allocation illustrated in FIG. In the above embodiment, the boundary address is
It is assumed that the start address and end address of area 1 and the end address of area 2 are used, and the start address of area 2 is calculated from the end address of area 1.
If one or more of the start address and the end address of the area 2 are designated and the others are obtained by calculation, it can be easily inferred that the content of the boundary address is not limited to the above.

The configuration of the embodiment of the present invention illustrated in FIG. 3 corresponds to the configuration of the image processing apparatus illustrated in FIG. 1, and the division mode and allocation of the storage space are illustrated in FIG. It is an example of the configuration in the case of the divided mode and allocation. Address specifying means for specifying an address for accessing the storage means for each access type of a plurality of devices, storage means for storing information indicating a boundary address between the divided areas, and the address specifying means Based on the address specified by the address and the boundary address indicated by the information stored in the storage means, monitoring which area the address specified by the address designating means is in, Any structure may be used as long as it is provided with an address control means for controlling the address designating means so that the next address becomes the start address of the area when it becomes equal to the end address.

[0018]

As described above, according to the present invention,
Since the storage space can be used as a plurality of variable-capacity ring buffer areas, the storage space can be used efficiently. Further, since it is provided with a means for monitoring in which area the address designated by the address designating means is present and setting the next address as the start address of the area when the address becomes equal to the end address of any area,
External control is not required, and the utilization efficiency of the external control device can be improved. Further, when the address designated by the address designating means becomes equal to the end address of any of the areas, when the address designating means is controlled so that the next address becomes the top address of the area, the start address and the end address of the area are controlled. Since one or both of them are calculated by the boundary address between the areas indicated by the information stored in the storage means, the number of registers for realizing a plurality of variable capacity ring buffer areas in the storage space can be calculated. Can be reduced. Therefore, the register access required for setting the positions and sizes of the plurality of variable capacity ring buffer areas can be reduced, and the control efficiency is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of an image processing apparatus including an address control apparatus according to the present invention.

FIG. 2 is a diagram showing an example of a storage space division mode and allocation.

FIG. 3 is a diagram showing a configuration example of an address control device according to the present invention.

[Explanation of symbols]

11 ... Image input means, 12 ... Image processing means, 13 ... Control means, 14 ... Storage means, 15 ... Image output means, 16 ... Address control means, 31 ... Register, 32 ... Address controller, 33-36 ... Address counter

Claims (1)

[Claims] 1. An image processing apparatus, comprising: storage means accessed by a plurality of devices for writing and reading data, wherein the storage space of the storage means is divided into a plurality of areas for use. An address designating means for designating an address for accessing the storage means for each individual access type, a storage means for storing information indicating a boundary address between the divided areas, and the address designating means. Based on the address to be designated and the boundary address indicated by the information stored in the storage means, it is monitored which area the address designated by the address designating means is in, and the address is the end of any area. When it becomes equal to the address, the address control means for controlling the address designating means so that the next address becomes the top address of the area. An address control device comprising: