JPH04336349A - Cache memory device - Google Patents

Abstract

PURPOSE:To obtain a cache memory which can make only data corresponding to an abnormal part ineffective without being made entirely ineffective if part of the memory array becomes abnormal. CONSTITUTION:Mask data which masks access data on a 2nd storage device 3 for a 3rd storage device 4 indicating whether or not the access data is effective is stored on a 4th storage device 5. Further, the cache memory device is provided with an AND circuit which ANDs the output values of the 3rd storage device 4 and 4th storage device 5. The mask data is set on the 4th storage device 5 at addresses where abnormality occurs to the 1st storage device 2 and 2nd storage device 3 and when a microprocessor accesses the abnormal address, an access data effectiveness signal 13 is made ineffective to prevent the access data 9 from being used.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a cache memory device, which is a high-speed memory device for a microprocessor.

0002

2. Description of the Related Art Conventionally, a cache memory device having a configuration as shown in FIG. 2 is generally known. In this configuration, a first storage device receives a partial field of address data 1 input to the cache memory device and outputs data 8 (hereinafter referred to as tag data 8) corresponding to the partial field. 2, a second storage device 3 that inputs a part of the address field and another field, and outputs data 9 corresponding to the sum of both fields; a third storage device 4 that inputs a field and outputs data 10 (hereinafter referred to as valid data) indicating whether the output data 9 of the second storage device 3 is valid; , a comparator 6 that compares the value of a field other than the field input to the second storage device 3 with the tag data 8 of the first storage device 2, and outputs matching data 12 when both data match. It has

In the conventional cache memory device configured as described above, previously accessed data is stored in the first storage device 2, second storage device 3, and third storage device 4. Corresponding data are output from the first, second and third storage devices 2, 3 and 4 into which the address data 1 is input. The comparator 6 compares the tag data 8 output from the first storage device 2 with the values of fields other than the fields input to the second storage device 3 in the address data, and determines whether the two match. In this case, matching data 12 is output. When both the matching data 12 and the valid data 10 are output, the microprocessor inputs the output data 9 of the second storage device 3, while outputting either the matching data 12 or the valid data 10. If not, data is accessed from other memory devices and the values in the first, second and third storage devices 2, 3 and 4 are updated.

0004

[Problems to be Solved by the Invention] However, in the above conventional configuration, the first storage device 2 and the second storage device 3
When an abnormality occurs in even one bit in the memory array, the entire cache memory device must be invalidated, resulting in a significant drop in the performance of the microprocessor.

The present invention has been made to solve the above problems, and an object thereof is to provide a cache memory device in which the performance of a microprocessor is less degraded.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention invalidates data only when accessing an address where an abnormality has occurred, and allows the cache memory device to function effectively at other times. shall be.

In other words, the specific solution of the present invention includes a first storage device into which some fields of an address are input and outputs a value corresponding to the some fields; fields are filled in and
a second storage device that outputs a value corresponding to the sum of both fields; and a value of a field other than the field input to the first storage device and the second storage device among the input addresses. and a comparison device that compares the output value of the first storage device with the output value of the first storage device, and a validity determination device that performs externally settable control of a signal indicating that the output value of the second storage device is valid. It is something that

[0008]

[Operation] With the above configuration, in the present invention, when an abnormality occurs in a certain address in the first storage device and the second storage device, the valid signal corresponding to that address is masked in advance. If set in the determination device, even if that address is accessed, the data corresponding to this address will always be invalidated by the validity determination device, and as a result, the microprocessor will access data to other storage devices. . Therefore, even if an abnormality occurs in part of the first storage device and the second storage device, there is no need to invalidate the entire cache memory, and the performance of the entire microprocessor does not deteriorate significantly.

[0009]

Embodiment An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is an input address to the cache memory device, 2 is a first storage device into which some fields of input address 1 are input and outputs values corresponding to these some fields, and 3 is an access device. A second storage device in which data is stored, in which the field input to the first storage device 2 and some other fields of the address are input, and a value corresponding to the sum of both fields. This outputs the following. Further, 4 is a third storage device storing data indicating whether or not the data stored in the second storage device 3 is valid, and 5 is a mask for the data stored in the third storage device 4. Mask data is set in advance in a portion corresponding to an address where an abnormality has occurred in the first storage device 2 and the second storage device 3.

Further, 6 is the input address field value other than the field of the address inputted to the first storage device 2 and the second storage device 3 and the output value of the first storage device 2 ( A comparator 7 serves as a comparison device for comparing tag data 8) to be described later, and a comparator 7 performs a logical product of the output value (valid data to be described later) 10 of the third storage device 4 and the output value of the fourth storage device 5. AND circuit, 8 is tag data output from the first storage device 2, 9 is access data output from the second storage device 3, 10 is valid data output from the third storage device 4, 11 is Mask data output from the fourth storage device 5, 12 is a comparator 6
13 is an access data valid signal output from the AND circuit 7. The fourth storage device 5 and the AND circuit 7 then use the mask data of the fourth storage device 5 to determine the valid data of the third storage device 4, that is, the output value of the second storage device 3. A validity determination device 14 is configured such that a signal indicating validity can be arbitrarily set as appropriate from the outside.

Next, the operation of the above embodiment will be explained. When an input address 1 is input to the cache memory device, a part of the field of the input address 1 is input to the first storage device 2, and tag data 8 corresponding to this part of the field is output. Further, the field input to the first storage device 2 and other fields of the input address 1 are input to the second storage device 3, the third storage device 4, and the fourth storage device 5, Access data 9, valid data 10 and mask data 1 corresponding to both fields
1 is output for each. The comparator 6 inputs the tag data 8 of the first storage device 2 and a field of the input address 1 that is not input to any of the storage devices 2 to 5, and when both inputs match, In addition to outputting a coincidence signal 12, the AND circuit 7 inputs valid data 10 and mask data 11, and outputs an access data valid signal 13 obtained by calculating the logical product of the input valid data 10 and mask data 11. The microprocessor is
Access data 9 is used when both the coincidence signal 12 and access data valid signal 13 are valid.

Here, if there is an address where an abnormality has occurred in the first storage device 2 and the second storage device 3, when the microprocessor accesses that address, the mask is removed from the fourth storage device 5. Data 11 is output, and as a result, the access data valid signal 13 of the AND circuit 7 becomes invalid, so that the microprocessor accesses data from another memory device. Therefore, if there is an address where an abnormality has occurred in the first storage device 2 and the second storage device 3,
Since the corresponding data is always invalidated and there is no need to invalidate the entire cache memory as in the past, the cache memory device can function effectively and the deterioration of the overall performance of the microprocessor can be suppressed to a small level. Can be done.

[0014]

[Effects of the Invention] As explained above, according to the present invention,
Even if an abnormality occurs in part of the first storage device and the second storage device, there is no need to invalidate the entire cache memory, and the cache memory device can function effectively, which improves the overall performance of the microprocessor. The list price can be kept low, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a cache memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of a conventional cache memory device.

[Explanation of symbols]

1 Address data 2 First storage device 3 Second storage device 4 Third storage device 5 Fourth storage device 6 Comparison device 7 AND circuit 8 Tag data 9 Access data 10 Valid data 11 Mask data 12 Match signal 13 Access data valid signal 14 Validity determination device

Claims (1)

[Claims] 1. A first storage device into which a partial field of an address is input and outputs a value corresponding to the partial field, and a first storage device into which a partial field of the address and another field are input, and outputs a value corresponding to the partial field. a second storage device that outputs a value corresponding to the added value; and a value of a field other than the field input to the first storage device and the second storage device among the input addresses and the first storage device. A comparison device that compares the output value of the second storage device with the output value of the second storage device, and a validity determination device that performs control that allows external setting of a signal indicating that the output value of the second storage device is valid. cache memory device.