JPH03175544A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the memory access time by simultaneously storing data within the range, which is indicated by the address of a register, in a cache memory after storing initial data in an external memory. CONSTITUTION:The processor is provided with an external bus 28, a cache memory 26, a data transfer means 23 which transfers data from the external bus 28 to the cache memory 26, a register 32 which designates the address range of the cache memory 26, comparators 33 and 34 to which the value of the register 32 and the address value of the cache memory 26 are inputted, and a write control means 35 for the control of write to the cache memory 26. Thus, data in the range indicated by the address of the register 32 is simulta neously stored in the cache memory 26 at the time of storing initial data in an external memory 30, and the operation is started in the hit state at the time of starting a processor, and data having a high frequency in use can be fixed in the cache memory 26 to increase the processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device using a cache memory.

2. Description of the Related Art Conventional data processing devices of this type use a magnetic disk or the like as an external storage device and a semiconductor memory as a main storage. The access time of this main memory is longer than that of processing devices whose performance has improved in recent years, and the performance of the processing device cannot be fully exploited. For this reason, cache memories are often used these days to speed up data transfer with storage devices. Since a memory with a short access time is used as the cache memory, the processing speed can be increased the next time data written once is read.

An example of a data processing device having a cache memory will be described with reference to FIG. In FIG. 5, 1 is a data processing device, which includes an address generation circuit 2, a data processing section 3, a human output buffer 4, a cache control circuit 5, a memory cache 6, an internal bus 7, and the like. 8 is an external bus that connects the input/output control device 9 to the input/output buffer 74, and is connected to the external memory ICI. 11 is an external storage device connected to the human output control device 9. The cache memory 6 is
It is used between the external memory IO and the data processing section 3. Initial data is transferred from the external storage device 11 to the external memory 10 via the input/output control device 9. The cache memory 6 receives data from the external bus 8 via the human output buffer 74.
Data transfer takes place. Data processing unit 3 can access cache memory 6 and external memory 10 via internal bus 7 and external bus 8.

Next, the operation of the data processing device 1 regarding the cache memory 6 will be explained. First, initial data is transferred. This is the storage of initial data from the external storage device 11 to the external memory 10.

During this time, the data processing device 1 is in a stopped state. Next, when the data processing device 1 is activated and becomes operational, an address for data is generated by the address generation circuit 2, and data corresponding to the address is read. When the data is in the cache memory 6, it is a hit, and when it is not, it is a miss. In the case of a miss, the contents of the cache memory 6 are rewritten, and the data read from the external memory 10 is written to the cache memory 6. Since the slow external memory 10 does not need to be used during a cache hit, data read time can be shortened.

Problems to be Solved by the Invention However, in the conventional configuration as described above, after the initial data is written to the external memory 10, the cache memory 6 becomes invalid. After data is stored, when the data processing device 1 is started up, it always starts with a cache miss. Furthermore, when the contents of the cache memory 6 are rewritten due to a miss, even data that is used less frequently may enter the cache memory, and the cache may not be used effectively.

Furthermore, in the case of a microprocessor with an on-chip cache memory 6, when the cache is hit, the read data is processed internally, so the value of the memory output is not known from the outside. For this reason, since the instruction code in the case of an instruction cache and the value of the data in the case of a data cache cannot be ascertained from the outside, it has not been easy to evaluate the part related to the cache memory of a microprocessor.

In view of these conventional problems, it is an object of the present invention to provide a data processing device that can increase the cache memory hit rate to speed up processing and easily evaluate the on-chip cache. shall be.

Means for Solving the Problems The present invention provides an external bus, a cache memory, data transfer means for transferring data from the external bus to the cache memory, a register that specifies the address range of the cache memory, and a register value and a cache memory. It is equipped with a comparator that inputs the address value of the memory, and write control means that controls writing to the cache memory.

The present invention also provides an external bus, an on-chip cache memory, a data transfer means for transferring data from the external bus to the on-chip cache memory, and a means for outputting data read from the on-chip cache memory to the external bus. It is provided with means for switching the direction of output of data on an external bus depending on cache misses and hits associated with instruction execution operations.

Effect of the Invention With the above-described configuration, the present invention can simultaneously store data in the range indicated by the address of the register in the cache memory when initial data is stored in the external memory. Since the process can be started quickly, it is possible to speed up the processing. Furthermore, since frequently used data is fixed in the cache memory, access to such data is accelerated. Also, for on-chip cache memory, the values output to the external bus according to hits or misses are observed to facilitate evaluation and enable measurement of memory access times in the same device.

Embodiment A first embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, 21 is a data processing device, which includes an address generation circuit 22, a data processing section 23, a human output buffer 724, a cache control circuit 25, and a memory cache 2.
6, internal bus 27, etc. 28 is an input/output control device 29
This is an external bus that connects the input/output buffer 724 to the external memory 30. 31 is the human output control device 2
This is an external storage device connected to 9. The address generation circuit 22, data processing section 23, and cache memory 26 are connected through an internal bus 27. internal bus 27
and the external bus 28 are connected by a human output buffer 724. The human output control device 29 controls the external storage device 31 and the external memory 30.

FIG. 2 shows a more detailed configuration of the cache control circuit 25 that controls the cache memory 26. In FIG. 2, 32 is a register that holds address values; 33.
34 is a comparator for comparing address values, 35 is a comparator 33
．． This is a write control circuit that receives the output of No. 34 as input.

Next, the operation of the above embodiment will be explained. First, initial data is written. Data is transferred from the external storage device 31 to the external memory 30 through the human output control device 29. At this time, an address value to be fixed in the cache memory 26 is written in the register 32 of the cache control circuit 25. The address value input to the cache control circuit 25 is constantly compared with the address value from the register 32 by comparators 33 and 34, and it is determined whether it is within the range set by the register 32. This results in
Only data in the specified address range is written to the cache memory 26.

Next, when the data processing device 21 is activated and becomes operational, the address of the data is generated by the address generation circuit 22, and this output is then input to the comparators 33 and 34 of the cache control circuit 25 for comparison. Let's do it. If the data falls within the range specified by the register 32, the data stored in the cache memory 26 is used. As a result, data in the address range specified at the time of startup is always in the hit state, allowing high-speed access. If the cache memory 26 is an instruction cache, frequently used programs are stored therein, and if it is a data cache, constants are stored therein, thereby speeding up the processing. Furthermore, when the data processing device 21 is in operation, it can be used as a normal cache memory by providing a mode in which no addresses are specified or by setting the range of the register 32 to zero.

Next, a second embodiment of the present invention will be described based on FIGS. 3 and 4. Third, 41 is a microprocessor as a data processing device, which includes an address generation circuit 42, a data processing section 43, an input/output buffer 44, a cache/input/output control circuit 45, and an on-chip cache memory 46. 48 is an external bus, and 49 is an external memory. The address generation circuit 42, data processing section 43, and on-chip cache memory 46 are connected to an internal bus 47.
connected through. Internal bus 47 and external bus 48
is connected to by an input/output buffer 744. The human output buffer 44 is controlled by a cache/input/output control circuit 45.

FIG. 4 shows a cache that controls on-chip cache memory 46j5 and human output buffer 744.

A more detailed configuration of the input/output control circuit 45 is shown. In FIG. 4, 50 is a cache control circuit, 51.52
is each person output buffer 7. in person output buffer 744.
Gates 53 and 54 control the buffers 51 and 52, respectively.

Next, the operation of the second embodiment will be explained. In the operating state of the microprocessor 41, a value is read from the on-chip cache memory 46 in the case of a cash hit. At this time, the direction of the input/output buffer 44 is output to the external bus 48 by enabling the signal DOEI from the gate 54 . In the event of a mishit, external memory 4
By enabling the signal OEI from the gate 53, data is input from the external bus 48 to the internal bus 47. In this way, input/output switching in the human output buffer 744 is determined based on hits/misses. As a result, even if the cache memory is on-chip, the value of data in use that has been read inside the microprocessor can be easily found from the external bus 48 of the microprocessor. If the on-chip cache memory 46 is an instruction cache, the instruction code can be observed, and if the on-chip cache memory 46 is a data cache, the data value can be observed. This is effective for microprocessor evaluation such as debugging. This circuit also allows measurement of the access time of the on-chip cache memory 46.

Effects of the Invention As is clear from the above explanation, according to the present invention, after initial data is stored in the external memory, data in the range indicated by the address of the register is simultaneously stored in the cache memory. If a certain area is always hit and stores frequently used data or instruction codes, memory access time can be shortened and processing speed can be significantly improved. Furthermore, since the data is written to the cache memory at the same time as the external memory, no extra time is required to store the initial data in the cache memory. Further, by controlling the input/output of the on-chip cache memory, the value of the cache memory in the operating state of the microprocessor can be known, which has the effect of facilitating evaluations such as debugging and measurement of access time.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a data processing device showing one embodiment of the present invention, FIG. 2 is a schematic block diagram showing the configuration of the cache control portion of FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a schematic block diagram showing the configuration of the cache/input/output control portion of FIG. 3, and FIG. 5 is a block diagram of a conventional data processing device. It is. 2... Data processing device, 41... Microprocessor (data processing device), 22.42... Address generation circuit, 23.43... Data processing unit, 24°44.
...Human output buffer 7.25.45...Cache control circuit, 26.46...Cache memory, 27.47
...Internal lotus, 28.48...External lotus, 29...
・Human output control device, 30.49...External memory, 3J
...External storage device, 32...Register, 33, 34
...Comparator, 35...Write control circuit, 50...
- Cache control circuit, 51.52... human output buffer, 53.54... gate.

Claims (2)

[Claims] (1) An external bus, a cache memory, a data transfer means for transferring data from the external bus to the cache memory, a register that specifies the address range of the cache memory, the value of the register, and the address of the cache memory. and write control means for controlling writing to the cache memory, and the output of the comparator is used as input to the write control means to write data from the external storage device onto the external bus. A data processing device that controls writing to the cache memory during data transfer and when the data processing device is in an instruction execution state. (2) an external bus, an on-chip cache memory, a data transfer means for transferring data from the external bus to the on-chip cache memory, and a means for outputting data read from the on-chip cache memory to the external bus; and means for switching the input/output direction of data on the external bus based on cache misses and cache hits associated with instruction execution operations.