JP2825983B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to an information processing apparatus having a cache and accessing a memory connected to a common bus via the common bus.

By the way, when a read miss occurs in a cache, a plurality of words are usually read in blocks from a memory and fetched into the cache. On the other hand, channel devices also use a common bus to transfer data from I / O to memory. Therefore, it is demanded to use the common bus efficiently and without causing a logical inconsistency.

[0003]

2. Description of the Related Art One of the exclusive control methods among a plurality of processors is Testa.
nd Set. In this method, reading from the semaphore area of the shared area and setting of the semaphore bit are performed by one access. When obtaining the occupation right of the shared area of the memory, the processor 1 performs Test and Set, and if the semaphore bit of the read data is “0”, the processor 1 can start accessing the shared area. (At this time, the semaphore bit in the semaphore area has already been set to "1.") After that, even if the processor 2 performs Test and Set, the read data is set to "1", so that the occupation right cannot be obtained and access is not possible. Can not.

After the access of the processor 1 is completed and "0" is written to the semaphore bit, the Tes of the processor 2 is
When the t and Set is performed, the semaphore bit read by the processor 2 is “0”, so that the processor 2 can start accessing. In this way, Test and
In the exclusive control using Set, while the processor 1 holds the occupation right, the processor 2 executes the Test and S
I had to have it while repeating the et.

[0005] In addition, for the memory read at the time of Test and Set, the cache cannot be used, and the memory must be read directly. In this case, if the semaphore bit is “1” in the first test and set, the semaphore area is fetched into the cache by performing a normal read instead of performing the test and set occupying the memory bus for the second and subsequent times, and A method is considered in which the semaphore bit becomes “0” by repeating data read.

That is, if the processor 1 writes "0" to the semaphore bit while repeating the cache read, the cache is invalidated.
The processor 2 shifts to the control of reading data on the memory, and can read the semaphore bit that has become “0”. Thereafter, Test and Set is performed to obtain the exclusive right. In this method, a common bus is connected to Test and Set.
You don't have to waste time by repeating.

However, this method has a contradiction in the following case. That is, the processor 2 performs Test and Se
Since the semaphore bit has already been set to "1" and the block data is read as a mishit read by performing a normal memory read, the semaphore bit is read by the processor 1 immediately after reading the first word having the semaphore bit.
And the processor 2 does not notice that the semaphore bit is "0" on the memory, and performs tag writing by reading the second word, the third word, and the fourth word.

Then, the semaphore bit on the memory becomes "0".
However, the data semaphore bit on the cache remains "1". This inconsistency arises from the fact that while the data is being cached, no validation is performed. Therefore, conventionally, during exclusive control, Test and Set has always had a method of always reading a semaphore bit from a memory.

On the other hand, in such a case, the priority of the memory access request of the processor performing the block read is set to the highest priority, and the other processor or the channel device interrupts the memory access during the block read. Although a method is conceivable, if the allowable overrun time of the I / O connected to the channel device is short, the common bus is occupied by the block-reading processor, and the memory cannot be accessed, causing an overrun. .

Therefore, a problem arises in that a system using this method cannot connect to an I / O having a short permissible overrun time. The present invention has been made in view of such a conventional problem, and can efficiently use a common bus without causing logical inconsistency, and also connect an I / O having a short overrun allowable time. It is an object of the present invention to provide a block read control method capable of performing the read operation.

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numerals 1 and 2 denote a plurality of processors having caches 3 and 4, reference numeral 5 denotes a channel device, reference numeral 8 denotes a memory accessed via a common bus 7, and reference numeral 17A denotes a memory hit of the processor 1 or 2. During the block read from the memory 8 at the time of
And 17B, a priority means for giving priority to a memory access request from the channel device 5 during the block read, and 11B.
A is invalidation means for invalidating the address-set data when the memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2 at that time.

[0012]

According to the present invention, in the event of a mishit in the memory read of the processor 1, the access of the other processor 2 is suppressed during the block read from the memory 8. Thus, the semaphore bit is not cleared by the memory write of the processor 2 during the block read of the processor 1.

Accordingly, even when the processor 1 reads the semaphore area in a block, the consistency between the contents of the cache 3 and the contents of the memory 8 is guaranteed. When there is a memory access request from the channel device 5 during the block read,
The request is prioritized. If the memory write address from the channel device 5 at that time hits the cache 3 of the processor 1, the address hit data is invalidated.

Therefore, the processor 1 can read the data in the memory 8 again because the cache 3 makes a mishit at the next access to the same area.
In this manner, the common bus 7 can be used efficiently without causing logical inconsistency, and I / Os with a short overrun allowable time can be connected.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 4 show a first embodiment of the present invention. In FIG. 2, reference numerals 1 and 2 denote processors, and the processors 1 and 2 have caches 3 and 4, respectively. Reference numeral 5 denotes a channel device, to which an input / output device (I / O) 6 is connected.

The processors 1 and 2 and the channel device 5 access the memory 8 via the common bus 7. In FIG. 2, REQ1 is a memory access request signal of the processor 1, REQ2 is a memory access request signal of the processor 2, REQC is a memory access request signal of the channel device 5, and LOCK is a memory access request of the other processors 1 and 2. This is the signal to be suppressed.

When the processor 1 reads a block, REQ
1 is output continuously, and a LOCK signal is output to the processor 2 at the same time when memory access is performed. Even if the processor 2 outputs the memory access request REQ2 during the block read of the processor 1, the memory access is suppressed because the LOCK signal from the processor 1 is input.

Therefore, the semaphore bit is not cleared by the memory write of the processor 2 during the block read of the processor 1. Therefore, even if the processor 1 performs block reading of the semaphore area, consistency between the contents of the cache and the contents of the memory is guaranteed. On the other hand, since the LOCK signal is not input to the channel device 5, the channel device 5
Is output, the memory access of the channel device 5 is performed on the way even while the processor 1 is performing block read.

Since the memory access request of the channel device is always given priority, an I / O 6 with a short overrun allowable time can be connected. Further, the exclusive control between the channel device 5 and the processors 1 and 2 does not use a semaphore area, so that there is no problem such as the exclusive control between the processors 1 and 2. That is, the channel device 5 transmits the I / O 6 to the memory 8
Memory area for data transfer to processors 1, 2
Is limited to the area specified by the control program (operating system), and therefore cannot be written to the semaphore area.

However, when the area written by the channel device 5 hits the caches 3 and 4 of the processors 1 and 2, the caches 3 and 4 must be invalidated. The invalidation area at this time is, of course, a different area from the area during block read. Next, the internal configuration of the processors 1 and 2 is shown in FIG. In FIG. 3, reference numeral 11 denotes a main memory interface controller, and reference numeral 12 denotes a monitoring directory (WatchingDirect) for monitoring a write to a main memory area registered in a directory of its own cache 3 or 4 by another processor 1, 2 or DMA.
ory).

Reference numeral 13 denotes an address bus in the main memory interface, 14 denotes a data bus in the main memory interface, 15 denotes a directory memory (tag memory) of its own cache 3 or 4, 16 denotes a buffer memory of the cache 3 or 4, and 17 denotes an MPU. , 18 are address registers, 19 is a data register, 20 is an address bus, 21 is a data bus, 22 is a hit signal, 23 is a hit number holding register, and the contents of the first stage are held in the second stage. , 24 are buffer memory address holding registers for holding the contents of the first stage in the second stage.

The address of the address register 18 is stored in the buffer memory address holding register 24, the tag memory 1
5 and main memory interface controller 11
In the case of a read hit, data is stored in the data register 19 from the buffer memory 16 of the cache 3, 4. In the case of a mishit, a mishit signal is supplied from the tag memory 15 to the main memory interface controller 11, and then data is stored in the data register 19 from the memory 8 via the data bus 14.

When a memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2, an invalid signal (INVL) is sent from the monitoring directory 12 of the main memory interface controller 1 to the tag memory 15. The data output and the address set is invalidated. The MPU 17 includes a processor 1
In the case where the memory read of the memory 2 is a mishit, during the block read from the memory 8, there is a memory access request from the channel device 5 in the middle of the block read and the inhibiting means 17 A for inhibiting the access of the other processors 1 and 2. At this time, it has a function as a priority means 17B for giving priority to the request.

The main memory interface controller 11 has a function as an invalidating means 11A for invalidating the address-set data when the memory write address from the channel device 5 hits the caches 3 and 4 of the processors 1 and 2. Have. Next, the operation will be described.

FIG. 4 is a time chart for explaining the operation. In FIG. 4, CLK is a synchronous clock for synchronizing the entire system, REQ1, REQ2, REQC, and LOC.
K and INVL are the above-described signals, TAGW is a tag write timing signal for caches 3 and 4, MAB and MDB
Are the buses described above, A1-1 is the address of the first read when the processor 1 reads the block, A1-2 is the address of the second read when the processor 1 reads the block, and A1-3 is the address of the processor 1. A4 is the address of the fourth read in the block read of the processor 1, A1-4 is the write address of the processor 2, and AC is the write address of the channel device 5. .

D1-1 is the first read data of the block read by the processor 1, D1-2 is the second read data of the block read by the processor 1, D1-3
Is the third read data of the block read by the processor 1, D1-4 is the fourth read data of the block read by the processor 1, DC is the write data of the channel device 5, and D2-1 is the write data of the processor 2. is there.

Here, the processor 1 changes the LOCK signal to τ
The transmission to the processor 2 during the period of 2 to τ5 prevents the processor 2 from interrupting and accessing the memory. However, overrun of the I / O 6 is prevented by permitting the memory access of the channel device 5 at τ4. At τ4, the INVL signal is sent to the tag memory 15, and the data whose address is set is invalidated.
Therefore, a miss occurs in the next cache read of the same area, and the processor 1 can read the data of the memory 8 again.

As described above, the common bus 7 can be used efficiently without causing logical inconsistency, and the I / O 6 having a short overrun allowable time can be connected.
Next, FIG. 5 and FIG. 6 are views showing a second embodiment of the present invention. In FIG. 5, the MPU 17 includes caches 3 and 4
Setting means 17C for setting the tag write timing at the time of reading the first word of the block read, and when the memory read of the processors 1 and 2 is a mishit and during the block read from the memory 8, the other processors 1 and 2
Alternatively, it has a function as a priority means 17D for giving priority to a memory access request from the channel device 5 when the memory access request is received.

The main memory interface controller 11 invalidates the address-set data when the memory write address from the other processor 1, 2 or the channel device 5 hits the cache 3, 4 during block reading. It has a function as means 11B. In this embodiment, the processors 1, 2
Is not used.

Next, the operation will be described with reference to a time chart shown in FIG. The reference numerals in FIG. 6 have the same meaning as in the above embodiment. The TAGW signal is set by the MPU 17 so as to be turned on when the word of the first word of the block read is read. By performing the tag write timing at the time of sending the first read address at the time of block read, even if data is written to the block-read memory area by the memory write of the processor 2 in the next cycle, the tag write is immediately performed. By performing the validation, it is possible to invalidate the data read from the subsequent block. In the next cache read in the same area, a miss occurs, and the first data in the memory 8, that is, the processor 2
Can read the written data.

Thus, the cache 3 and the memory 8
Data mismatch can be prevented. That is, by performing tag writing using τ2, the processor 2
Even if the block read area of the processor 1 is hit by the memory write of (1), the invalidation (IN
By performing (VL = 1), the cache 3 for block reading is invalidated, so that the processor 1 reads the data in the memory 8 again because the cache 3 miss-hits at the next access to the same area. By the (τ
9 to τ12), logical inconsistency does not occur.

In this embodiment, the same effect as in the above embodiment can be obtained. Next, FIGS. 7 and 8 show a third embodiment of the present invention. In FIG. 7, the MPU
17 has a function as a stopping means 17E for stopping the reading of the remaining words of the block reading when the address-set data is invalidated in addition to the second embodiment.

Next, FIG. 8 shows a time chart of this embodiment. The reference numerals in FIG. 8 have the same meaning as in the above embodiment. When the address written by the processor 2 hits the block being read by the processor 1 during the block read of the processor 1, the block is invalidated and the remaining words of the subsequent block read by the processor 1 are deleted. Cancel and move to the next operation.

If the block read area is a semaphore area, the semaphore bit is "1" in the first read, so that the same area is read again. , Immediately after τ5. That is, since the invalidation was performed at τ3, block reading after τ5 is stopped, and block reading is newly started again from τ6.

In this embodiment, the same effects as in the above embodiment can be obtained.

[0036]

As described above, according to the present invention, the common bus can be used efficiently without causing logical inconsistency, and the system performance can be improved.
Also, I / O with a short overrun allowable time can be connected, and system applicability can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an information processing apparatus according to a first embodiment of the present invention.

FIG. 3 is an internal configuration diagram of a processor.

FIG. 4 is a time chart for explaining the operation;

FIG. 5 is a diagram showing a processor according to a second embodiment of the present invention.

FIG. 6 is a time chart for explaining the operation;

FIG. 7 is a diagram showing a processor according to a third embodiment of the present invention.

FIG. 8 is a time chart for explaining the operation;

[Description of Signs] 1, 2: Processor 3, 4: Cache 5: Channel Device 6: Input / Output Device (I / O) 7: Common Bus 8: Memory 11: Main Memory Interface Controller 11A, 11B: Invalidation Unit 12: Monitoring directory 13: Address bus 14: Data bus 15: Directory memory (tag memory) 16: Buffer memory 17: MPU 17A: Suppression means 17B, 17D: Priority means 17C: Setting means 17E: Stop means 18: Address register 19: Data Register 20: Address bus 21: Data bus 22: Hit signal 23: Hit number holding register 24: Buffer memory address holding register

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Odawara 1015 Ueodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Eiji Kanaya 1015 Kamiodanaka Nakahara-ku Kawasaki-shi Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-58-212694 (JP, A) JP-A-62-266634 (JP, A) JP-A-64-7144 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , (DB name) G06F 12/08 G06F 15/16 320

Claims (3)

(57) [Claims] 1. An information processing apparatus comprising a processor having a cache and accessing a memory connected to a common bus via the common bus, wherein a predetermined area of the memory is accessed by a memory read mishit. A deterrence means for deterring memory access of another processor during block reading from the memory; and the predetermined area from the input / output device during the block reading.
When there is a memory access request for an area other than
And characterized in that it has a priority means for giving priority to the request, and a disabling means for disabling the address set data when the memory write address of the memory access request from the output device is hit in the cache Information processing device. 2. An information processing apparatus comprising a processor having a cache and accessing a memory connected to a common bus via the common bus, wherein a timing of tag writing of the cache is read from the memory by a block read from the memory. Setting means for setting at the time of reading of the first word of a memory, and when a memory access request is received from another processor or an input / output device during block reading from the memory due to a memory read miss, the request is prioritized. Priority means for causing a memory access address of a memory access request from the other processor or the input / output device to hit the cache during the block read, and invalidating means for invalidating the address-set data. An information processing apparatus characterized by the above-mentioned. 3. An apparatus according to claim 1, further comprising: a stop unit for stopping reading of the remaining words of the block read when the address-set data is invalidated. After the stop of the block read by the stop unit, the block read of the same area is performed again. 3. The method according to claim 2, wherein
An information processing apparatus according to claim 1.