JP2677706B2 - Memory access control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A memory access control circuit for a 2-cycle cache, which aims to enable quick and accurate execution of the next memory access processing that mishit-reads to the cache. In a 2-cycle cache memory access control circuit that sends an address in 1 cycle and transfers data in the 2nd cycle while overlapping with the 1st cycle of the next access, if a miss hit occurs in the 1st cycle, the 2nd cycle STINH that generates a signal to suppress the stage transition of
The generation circuit and the memory access request enable signal (MRQOK signal) are turned off at the time of a miss, and the MRQOK signal is turned on from the cycle immediately before the last data read from the main memory reaches the cache memory. STINH when the circuit and the MRQOK signal goes from off to on
A STINH suppression circuit for stopping the stage transition suppression signal of the generation circuit is provided.

[Industrial applications]

According to the present invention, in a two-cycle cache memory access method in which an address is transmitted in the first cycle, and data is transferred in the second cycle by overlapping with the first cycle of access next, in the case of a miss hit in the cache memory, The present invention relates to a memory access control circuit for performing the next access quickly and accurately.

[Conventional technology]

In many data processing systems, a cache device is added as a means for substantially shortening the access time to the main memory. Especially in a system requiring high speed, in order to efficiently use the cache memory, a 2-cycle access pipeline control in which a data transfer cycle and an address transmission of the next access are overlapped is adopted. There is.

In this 2-cycle access pipeline control, since the address of the next access is sent while the hit determination of the sent address is being performed, the control in the case of a mishit becomes complicated. There will be a considerable overhead before resuming access to.

Next, a conventional 2-cycle memory access control system will be described with reference to FIGS. FIG. 6 is an explanatory diagram of stage transition, FIG. 7 is an explanatory diagram of a conventional memory access control system, FIG. 8 is an operation timing chart of a conventional memory access control circuit, and FIG. 9 is a conventional memory access control system. It is explanatory drawing of the operation timing chart at the time of a mishit and when there is an invalidation.

In FIG. 7, reference numeral 21 denotes a main memory interface controller (indicated by an MM interface controller), which performs interface control between a main memory (not shown) and a memory access control circuit. Reference numeral 211 denotes a monitoring directory provided in the MM interface controller 21, which monitors a write to the main memory area registered in the directory of its own cache by another processor or DMA (direct memory access).

MAB is an address bus between the MM interface controller 21 and the main memory, and MAD is a data bus between the MM interface controller 21 and the main memory.

Reference numeral 22 denotes a directory memory, which is also called a tag memory and stores the address of data registered in the cache memory.

HIT is a hit signal that supports a hit in the cache memory, and indicates 1 when a hit occurs and 0 when a miss hit occurs.

23 is a hit number holding register (indicated by the HIT register)
The hit information output from the directory memory 22 in the first cycle is stored. Directory memory 22
If is composed of a plurality of blocks, the hit information indicates the number of the hit block. This hit information selects the memory area corresponding to the block in the cache memory.

Reference numeral 24 is a buffer memory for cache (hereinafter referred to as cache memory), which is composed of a high-speed memory device such as a bipolar transistor, and registers the data of the accessed main memory.

Reference numeral 25 is a cache address holding register (indicated by a CMA register), which stores an address for accessing the cache memory 24 sent in the first cycle, and stores the next second address.
Hold until cycle.

A processor 26 executes a stage process in each cycle and controls the operation of the entire system.

An address register 261 is provided in the processor 26, and stores addresses for accessing the main memory, the directory memory 22, and the cache memory 24.

A data register 262 is provided in the processor 26 and stores data read from the cache memory 24 or the main memory.

AB is MM interface controller 21 and processor 26
CB is a control signal bus for transferring various control signals, and DB is a data bus for transferring data between the MM interface controller 21 and the processor 26.

INVL is an invalidation signal that invalidates the data registered in the cache memory 24. When this invalidation signal is received, the directory memory 22
An invalidation flag (not shown) is set in the area corresponding to the invalidation target data area.

A memory access control circuit 30 is provided in the MM interface controller 21 and receives a command from the processor 26 to control memory access to the main memory. Regarding various control signals generated by the memory access control circuit 30 and the memory access control operation,
The operation will be described later. Various control signals shown in parentheses in the block of the memory access control circuit 30 indicate various control signals generated inside the memory access control circuit 30.

Next, the stage transition controlled by the memory access control circuit of FIG. 7 will be described with reference to the sixth stage transition explanatory diagram.

In the first memory request stage in FIG. 6, the processor 26 performs a process of transmitting a memory access request signal MRQ requesting access to a main memory (not shown).

When the access request to the main memory is accepted, in the next first stage, a process of transmitting an address for accessing the main memory and a hit determination process for the cache memory are performed. STG1 is a first stage signal that activates the first stage and is generated by the memory access control circuit 30.

In the next second stage, processing for transferring the hit data to the cache memory is performed. STG2 is second
This is the second stage signal that activates the stage and is generated by the memory access control circuit 30.

Next, referring to the operation timing chart of FIG.
The memory access control operation will be described. In FIG.
CLK1 is a clock that regulates the timing of each operation performed in the memory access control circuit 30, and is generated in synchronization with the system clock common to the system. τ ₁ , τ ₂ etc. are
Each cycle of the clock CLK1 is shown (FIG. 8 (a)).

When accessing the main memory (not shown), the processor 26 sends a memory access request signal MRQ at the memory request stage (FIG. 8 (b)). Now, in the cycles τ ₁ , τ ₂ and τ ₃ of the clock CLK1, the memory access request MRQ is continuously generated. As shown in the drawing, the memory access request MRQ is generated.
, MRQ and MRQ (FIG. 8 (b)).

When the memory access request permission condition is satisfied for the first memory access request signal MRQ issued in τ ₁ cycle, the memory access request circuit 30 permits the memory access request to permit the memory access request in the same τ ₁ cycle. The permission signal MRQOK (indicated by the MRQOK signal) is turned on (FIG. 8 (c)).

When the MRQOK signal is turned on, the memory access control circuit 30 generates the first stage signal STG1 (indicated by STG1) in the next cycle τ ₂ in synchronization with the clock CLK1 and outputs it via the control signal bus AB. It is sent to the processor 26 (FIG. 8 (d)).

Upon receiving this first stage signal STG1, the processor
26 performs the first stage processing in the second cycle τ ₂ , sends out the address for accessing the main memory in the address register 261 via the address bus AB (FIG. 8 (f)), and further caches The hit judgment for the memory 24 is performed.

That is, the address sent by the processor 26 first accesses the directory memory 22. If the directory memory 22 has an address corresponding to the address to be accessed, the hit signal HIT becomes 1 to indicate that the cache memory has been hit. If there is no address corresponding to the accessed address in the directory memory 22, the hit signal HIT becomes 0. It is instructed that there is a mishit in the cache memory.

The hit signal HIT is sent to the memory access control circuit 30 via the MM interface controller 21. Further, the hit information of the cache memory is stored in the HIT register 23. If the directory memory 22 is composed of a plurality of blocks, this hit information indicates the number of the hit block. The hit information in the HIT register 23 is sent to the cache memory 24. When the hit signal HIT is 1 (hit the cache memory), the area of the cache memory 24 corresponding to the block number of the hit directory memory 22 is selected. .

Hereinafter, description will be given separately for the case where the cache memory 24 is hit and the case where there is a miss hit.

(1) When the cache memory is hit When the cache memory 24 is hit, that is, when the hit signal HIT is 1, the memory access control circuit 30
Is the clock signal CLK1 that defines the operation timing of the circuit.
In the next cycle τ ₃ in synchronization with the second stage signal
STG2 (indicated by STG2) is generated and sent to the processor 26 via the control signal bus CB (FIG. 8 (e)).

When receiving this second stage signal STG2, the processor
As shown in FIG. 6, 26 performs the second stage processing in the second cycle τ ₃ , reads the hit data in the cache memory 24, and transfers it to the data register 262 of the processor 26 via the data bus DB.

On the other hand, in this cycle τ ₃ , the first cycle (first stage) for the next memory access request signal MRQ overlaps with the processing of the second cycle (second stage) for the first memory access request signal MRQ.
Is performed (see STG1 in FIGS. 6 and 8 (d) and STG2 in (e)).

First cycle of next memory access request signal MRQ (first stage STG1 of τ ₃ cycle in FIG. 8 (d))
When the cache memory 22 is hit at,
_{In four} cycles, the second cycle of the memory access request signal MRQ, that is, the processing of the second stage STG2 is executed.

Similarly, when the cache memory is hit, each process of the first stage STG1 and the second stage STG2 for each memory access request signal MRQ is continuously executed (not shown).

(2) When there is a miss in the cache memory Now, the memory access request signal MRQ made at τ ₂
In the processing of the first stage STG1, if the address sent from the processor 26 miss-hits the cache memory 24, the hit signal HIT becomes 0 in the cycle τ ₂ (FIG. 8 (j)).

In the memory access control circuit 30, the hit signal HIT is 0
In the case of (miss hit), the clock inhibition signal CLKSP is generated in τ ₃ cycle.

Further, the memory access control circuit 30 uses the hit signal HIT
Is 0 (miss) and the first stage STG1 of the continuous memory access request signal MRQ is on (τ ₃ cycle in FIG. 8 (d)), the stage transition inhibition signal STINH from τ ₄ cycle. Is turned on (Fig. 8 (1)).

As a result, the first stage signal STG of the memory access request signal MRQ output from the memory access control circuit 30.
The value of 1 continues to hold the value 1 after τ ₃ cycles (FIG. 8 (d)), and the second stage signal STG2 of the memory access request signal MRQ continues after τ ₃ cycles. And holds the value 1 (FIG. 8 (e)).

Further, as described above, the generation of the clock after τ ₄ is suppressed by the generation of the clock suppression signal CLKSP in the τ ₃ cycle, and the control operation of the memory access control circuit 30 after the τ ₄ cycle is temporarily suspended. Done (8th
(N) and (a)).

While the control operation of the memory access control circuit 30 is temporarily suspended due to the miss hit in the cache memory 24, the MM interface controller 21 reads the miss hit data from the main memory (not shown),
While transferring to the processor 26 via the data bus DB, register this read data in the cache memory 24,
A process of registering tag information such as the address in the directory memory 22 is performed. This data transfer process is performed by τ _{4 to} τ ₆
It takes place between cycles.

Data read from the main memory is performed in block units, and a plurality of words (in the figure, D-1 to D in the figure) including the data hit to the memory access request signal MRQ are hit.
-4 words) are read and transferred to the processor 26 and the cache memory 24 (FIG. 8 (g)).

When data of each block unit is read from the main memory, block read signals BLKRD1 to BLKRD4 are sent from the MM interface controller 21 to the memory access control circuit 30 corresponding to the data words D-1 to D-4. However, block read signals BLKRD3 and BRKRD4 are shown in FIGS. 8 (h) and (i).

Processor when the first data D-1 is transferred
Since 26 can move to the next processing, the memory access control circuit 30
The control of the clock CLK may be stopped and its control may be restarted. Therefore, the MM interface controller 21 sets the start signal START to 1 (ON) (τ in FIG. 8 (p)).
₇ ).

When the start signal START becomes 1, the memory access control circuit 30 causes the clock inhibition signal CLKS in the next τ ₈ cycle.
The clock CLK is restarted by setting P to 0 (Fig. 8 (a)).
And τ ₈ cycles of (n)).

When the transfer of the mishit data is completed, that is, when the data D-4 is transferred (the end of the τ ₁₁ cycle), it is not necessary to suppress the stage transition, and the stage transition is started from the next τ ₁₂ cycle. It doesn't matter.

However, when the block read signal BLKRD3 indicating the transfer period of the data D-3 of the third word of the block read is turned on at τ ₁₀ , the memory access control circuit 30 makes the next τ ₁₁
The stage transition inhibition signal STINH is set to 0 (off) in the next τ ₁₂ cycle which is delayed by 1 cycle from the above (FIG. 8 (l),
The reason for delaying 11 cycles after τ ₁₁ is:
I'll explain later).

As a result, the first stage STG1, which is a stage process related to the memory access request signal MRQ, remains on for up to τ ₁₂ cycles, and a valid hit determination is performed at τ _12, which enables the hit determination to the cache memory 24. , Τ ₁₃ cycles, the second stage STG2 is normally executed (FIGS. 8 (d), (e), (j),
(K)).

In the τ ₁₃ cycle, similarly to the case of the τ ₃ cycle described above, the second cycle processing (second stage STG2) for the memory access request signal MRQ and the first cycle processing (first stage) for the next memory access request signal MRQ2 (first Stage ST
G1) is performed in parallel (Figs. 8 (d), (e),
(J), (k)).

Next, the reason why the stage transition inhibition signal STINH is set to 0 (OFF) in the next τ ₁₂ cycle which is one cycle behind the τ ₁₁ cycle will be described with reference to FIG.

FIG. 9 shows an operation timing chart similar to FIG. 8. The meaning of each symbol of (a) CLK to (p) START and the operation contents up to τ ₈ cycle are the same as those of FIG. Is the same.

However, block read signals BLKRD2 and BLKRD3 are shown in FIGS. 8 (h) and (i). Continued (q)
PINVL is an invalidation request signal, and is a signal requesting that data registered in the cache memory 24 be specified and that it be invalidated. The invalidation request signal PINVL is generated by the monitoring directory 211 of the MM interface controller 21 and sent to the memory access control circuit 30.

Further, the INVL of the next (r) is an invalidation signal for invalidating the data registered in the cache memory 24, as described above, and when the invalidation signal is received, it is stored in the directory memory 22. An invalid flag (not shown) is set in the area corresponding to the invalidation target data area.

When the transfer of the data D-4 of the memory access request signal MRQ ends at τ ₁₁ , when the data transfer of the memory access request signal MRQ is to be performed in the next τ ₁₂ cycle, the memory access control circuit 30 performs block read. When the block read signal BLKRD2 indicating the transfer period of the data D-2 of the second word of is turned on at τ ₉ , the next τ ₁₀
The stage transition inhibition signal STINH is set to 0 (OFF) in the next τ ₁₁ cycle which is delayed by 1 cycle from the above (STEP (1) in FIG. 9).

As a result, the first stage STG1, which is a stage process related to the memory access request signal MRQ, remains in the ON state until τ ₁₁ cycles, and the hit determination for the cache memory 24 becomes possible, and a valid hit determination is performed at τ _12. , Τ ₁₂ cycle, the second stage STG2 is normally executed (FIGS. 8 (d), (e), (j),
(K)).

In the τ ₁₂ cycle, similar to the case of the τ ₃ cycle described above, the second cycle processing (second stage STG2) for the memory access request signal MRQ and the first cycle processing (first stage) for the next memory access request signal MRQ (first Stage STG
And 1) are performed in parallel (Figs. 8 (d), (e),
(J), (k)).

However, if the memory transfer request signal MRQ is transferred to the main memory area registered in the directory memory 22 of its own cache memory 24 by another processor or DMA before τ ₁₂ cycles before the data transfer is performed. If so, watched directory
211 indicates the validation request signal PINVL at τ ₁₀ .
Is generated and sent to the memory access control circuit 30.

Since the invalidation request must always be given priority over the stage processing, the memory access control circuit 30
When the validation request signal PINVL is received, the next τ
_{In 11} cycles, an invalidation signal INVL is generated to invalidate the directory memory 22.

Therefore, the processor 26 cannot execute the processing of the first stage STG1 of the memory access request signal MRQ in the τ ₁₁ cycle. As a result, the cache memory 24
It becomes impossible to make a hit determination with respect to, and the subsequent processing becomes impossible.

Therefore, even if such an invalidation occurs, in order to enable the stage processing up to that point to be normally executed after performing the invalidation processing on the cache memory 24 and the directory memory 22, the conventional memory access control is performed. , As explained in FIG.
The transfer of data D-1 to D-1 at the time of a mishit has ended
Stage transition suppression signal STINH from τ ₁₂ cycle next to ₁₁
Is turned off and the stage processing is restarted.

As a result, even if the invalidation request signal PINVL is generated in the τ ₁₀ cycle, a predetermined invalidation process is performed on the directory memory 22 in the next τ ₁₁ cycle, and after the subsequent τ ₁₂ cycle, FIG. As described above, each stage processing up to that point is normally executed.

The hit delay signal HITD shown in (k) of FIG.
Is a signal obtained by delaying the hit signal HIT by one cycle, and the first stage effective signal STG1V is a signal indicating that the first stage processing was effective. Both signals are generated inside the memory access control circuit 30, in which
Stage 1 valid signal STG1V and hit delay signal HITD
Is used to generate the stage transition inhibition signal STINH.

[Problems to be solved by the invention]

As described above, the conventional memory access control is such that when a miss hit occurs in the cache memory, even if an invalidation occurs in the cache memory when the miss hit data is read from the main memory and transferred, In order to allow the stage control to be executed normally, the stage processing is restarted with a delay of one cycle from the cycle in which the transfer of the mishit data is completed.

For this reason, although the probability that invalidation will normally occur when a miss hits the cache memory, an extra 1 cycle is always inserted at the time of a miss hit, and as a result, subsequent processing is delayed by that amount, and the entire process is delayed. However, there was a problem that the efficiency of memory access processing deteriorates.

The present invention, when there is a miss hit in the cache memory,
An object of the present invention is to provide an improved memory access control circuit that improves the efficiency of memory access processing by sending the start cycle of stage processing that is restarted after the end of data transfer of mishit data only when invalidation occurs. And

[Means for solving the problem]

Means adopted by the present invention to solve the above-mentioned problem will be described with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, reference numeral 10 denotes an entire memory access control circuit, which sends out an address in the first cycle, performs data transfer in the second cycle by overlapping with the first cycle of the next access, and in the first cycle. The sent address and the hit information and hit block number information obtained by accessing the tag memory by the address are held for the second cycle, and if the hit information indicates a hit, the held information is held in the second cycle. A cache memory (not shown) is accessed by a block number and an address. When a mishit occurs, a block read is performed by the address from the main storage and the cache memory is accessed in two cycles.

Reference numeral 11 denotes a stage transition suppression signal generation circuit (hereinafter referred to as STINH generation circuit), which suppresses the stage transition of the second cycle when the hit information output in the first cycle indicates a mishit. Performs processing to generate the signal STINH.

12 is a memory access request permission signal generation circuit (hereinafter, MR
The cycle just before the last data read from the main storage by the above address to the cache memory is turned off by turning off the memory access request enable signal MRQOK (shown by the MRQOK signal) at the time of a mishit. The process of turning the MRQOK signal from off to on is performed. The MRQOK signal is as described above.

Reference numeral 13 is a stage transition inhibition stop circuit (hereinafter referred to as STINH stop circuit), which detects that the MRQOK signal is turned from OFF to ON and stops the stage transition inhibition signal STINH generated by the STINH generation circuit 11. Perform processing.

14 is a memory access request permission suppression circuit (hereinafter, MRQOK
MRQOK generated by the MRQOK generation circuit 12 in order to perform invalidation processing in the cycle when a request to invalidate its own cache memory is made in the cycle in which the MRQOK signal is turned on. Performs processing to prevent the signal from turning on.

(Operation)

The effect of the present invention is (1) when the cache memory is hit, (2) when the cache memory is miss-hit and there is no validation request, and (3) when the cache memory is missed and there is an invalidation request. Each will be explained separately.

(1) When the cache memory is hit During the normal operation of hitting the cache memory, the memory access control circuit 10 controls the memory access in two cycles.

That is, in the first cycle, an address for accessing the main memory (not shown) is sent out, and in the second cycle, the read data is transferred from the main memory while overlapping with the first cycle of the next access.

The address sent in the first cycle and the disk memory are accessed by the address, and the obtained hit information and address information (for example, hit block number information) are held for the second cycle.

If the hit information indicates a hit to the cache memory, the cache memory (not shown) is accessed by the held address information in the second cycle,
Read the specified data.

Hereinafter, for each access, the above-mentioned two-cycle memory access control is repeated in a relationship that the second cycle of the current access (data transfer stage) and the first cycle of the next access overlap (address transmission stage).

(2) When there is a miss hit in the cache memory and there is no validation request The STINH generation circuit 11 is a stage that suppresses the stage transition of the second cycle when the bit information output in the first cycle indicates a miss hit. A transition inhibition signal STINH is generated to prevent the stage processing performed by the processor (not shown) in the second cycle from transitioning.

On the other hand, the MRQOK generation circuit 12 turns off the MRQOK signal at the time of a mishit to interrupt the subsequent memory access control of the memory access control circuit 10.

While the memory access control in the memory access control circuit 10 is suspended, the processor performs a process of reading the mishit data from the main memory according to the address information, for example, in block units.

The MRQOK generation circuit 12 outputs the MR in the cycle immediately before the last read data reaches the cache memory.
Turn the QOK signal from off to on.

The STINH stop circuit 13 is the same as the one generated by the MRQOK generating circuit 12.
Detecting that the MRQOK signal has changed from OFF to ON, the STI
The stage transition inhibition signal STINH generated by the NH generation circuit 11 is stopped.

As a result, the processing of the first cycle of the next access is executed immediately after the cycle following the cycle in which the block read of the mishit data from the main memory is completed.

In this way, when a miss hit is made in the cache memory but there is no invalidation request, when the read of the miss hit data from the main memory is completed, the next access is immediately executed without opening the next one cycle as in the conventional method. Since the processing of the first cycle is executed, useless cycles are eliminated and the memory access processing efficiency can be improved.

(3) When there is a miss hit in the cache memory and there is an invalidation request When a miss hit occurs in the cache memory and an invalidation request for the cache memory occurs when the miss hit data is read and transferred from the main memory, that is, When a request to invalidate the own cache memory is made in the cycle in which the MRQOK signal is turned on again, the MRQOK suppression circuit 14 of the memory access control circuit 10
In order to perform invalidation processing in the cycle, the MR
Processing is performed to prevent the MRQOK signal generated by the QOK generation circuit 12 from turning on.

As a result, in the cycle next to the cycle in which the block read of the mishit data from the main memory is completed, the processing of the first cycle of the next access is suppressed, and the invalidation processing regarding the cache memory area that is the invalidation target is performed. Is done.

When the invalidation process is completed, the process for the next access is normally executed from the next cycle.

As you can see, there was a miss in the cache memory,
When the block read of the mishit data from the main memory is completed only when there is an invalidation request, the next cycle is opened and the invalidation processing is performed as in the conventional method.

In the case of DMA transfer, invalidation requests may be generated continuously, but in that case, it is possible to prevent the MRQOK signal generated by the MRQOK generation circuit 12 from turning on while the invalidation requests are continuous. Processing is performed.

As a result, according to the number of validation requests,
A cycle for performing the invalidation process is inserted, and the invalidation process for continuous invalidation requests can be normally performed.

As described above, in the present invention, when a miss hit occurs in the cache memory, the stage processing is restarted with a delay of one cycle after the end of the data transfer of the miss hit data only when the invalidation request occurs. When there is no, there is no wasted cycle, and the memory access processing efficiency can be improved.

In addition, since the stage processing is restarted with a delay of the number of cycles corresponding to the number of validation requests, even if invalidation requests occur continuously,
These invalidation processes can be normally processed, and the stage process for each interrupted access request can be normally restarted.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. FIG. 2 is an explanatory diagram of a configuration of a memory access control system in which a memory access control circuit of an embodiment of the present invention is used, and FIG. 3 is an explanatory diagram of a configuration of an embodiment of the present invention.
FIG. 4 is an operation timing chart of the same embodiment when there is no validation request, and FIG. 5 is an operation timing chart of the same embodiment when there is an invalidation request. The stage transition explanatory diagram of FIG. 6 is as described above.

(A) Configuration of the Embodiment In FIG. 2, the configuration other than the memory access control circuit 10 is the same as the configuration of the conventional memory access control system described in FIG. Will be described with the same reference numerals.

That is, reference numeral 21 is a main memory interface controller (MM interface controller), which performs interface control between a main memory (not shown) and a memory access control circuit. Reference numeral 211 denotes a monitoring directory provided in the MM interface controller 21, which monitors a write to the main memory area registered in the directory of its own cache by another processor or DMA (direct memory access).

MAB is an address bus between the MM interface controller 21 and the main memory, and MAD is a data bus between the MM interface controller 21 and the main memory.

Reference numeral 22 denotes a directory memory in which address information of data registered in the cache memory and information indicating whether the data is valid or invalid are registered.

HIT is a hit signal which indicates that the cache memory 24 has been hit, and when hit, indicates 1 and
If there is a mis-hit, specify 0.

23 is a hit number holding register (indicated by the HIT register)
The hit information read from the directory memory 22 in the first cycle is stored.

A cache memory 24 is composed of a high speed memory device such as a bipolar transistor, and temporarily stores the accessed data of the main memory.

A cache address holding register (CMA register) 25 stores the address for accessing the cache memory 24 sent in the first cycle, and holds it until the next second cycle.

A processor 26 executes a stage process in each cycle and controls the operation of the entire system.

An address register 261 is provided in the processor 26, and stores addresses for accessing the main memory, the directory memory 22, and the cache memory 24.

A data register 262 is provided in the processor 26 and stores data read from the cache memory 24 or the main memory.

AB is MM interface controller 21 and processor 26
CB is a control signal bus for transferring various control signals, and DB is a data bus for transferring data between the MM interface controller 21 and the processor 26.

INVL is an invalidation signal that invalidates the data registered in the cache memory 24. When this invalidation signal is received, the directory memory 22
An invalidation flag (not shown) is set in the area corresponding to the invalidation target data area.

The memory access control circuit 10 is provided in the MM interface controller 21, receives a command from the processor 26, and controls the memory access to the main memory. The operation of the memory access control circuit 10 is performed in synchronization with the clock CLK0, which is generated in synchronization with the system clock SCLK.

The various control signals generated by the memory access control circuit 10 are the same as those described in the operation timing charts of the conventional memory access control circuits of FIGS. 8 and 9, but the following memory access control circuit Also in the section of the configuration of the embodiment, the description will be made as needed.

Next, the configuration of one embodiment of the memory access control circuit of the present invention will be described with reference to FIG.

In FIG. 3, STINH generation circuit 11 and MRQOK generation circuit 1
2, STINH stop circuit 13, and MRQOK suppression circuit 14 are as described in FIG.

The STINH generation circuit 11 is composed of an AND circuit 111 and a JK flip-flop (hereinafter referred to as JKFF) 112. AND circuit 11
The AND output of the first stage signal STG1 *, the HITD signal, and the STGIV signal, which will be described later, is input to 1, and the AND output is input to the J terminal of the JKFF112.

JKFF112 is a clock CLK0 synchronized with the system clock
, Which operates in synchronism with the MRQOK suppression circuit 14
The MRQOK stop signal is input, the output terminal Q generates the stage transition inhibition signal STINH, and the inverted output terminal generates the inverted stage transition inhibition signal * STINH.

The MRQOK generation circuit 12 includes an inverter 121, an AND circuit 122 and
Composed of JKFF123. The AND circuit 122 includes an inverter 121.
The hit signal HIT and the first stage signal STG1 inverted by are input, and the AND output is input to the J terminal of JKFF123.

The JKFF123 operates in synchronization with a clock CLK1 described later, a block read signal BLKRD2 for instructing the second block read is input to its K terminal, and an MRQOK ₀ signal is generated at its inverted output terminal. The MRQOK ₀ signal becomes 1 (on) when the block read signal BLKRD2 of the K terminal becomes 1 (on), and becomes 0 (off) when the input of the J terminal becomes 1 (on).

The STINH stop circuit 13 is a D flip-flop (hereinafter, DFF).
131) and an AND circuit 132.

The memory access request permission signal MR is connected to the D terminal of DFF131.
QOK is entered. The output from the inverting output terminal of the DFF 131 and the memory access request permission signal MRQOK are input to the AND circuit 132, and the AND output is input to the K input of the STINH generation circuit 112. With this configuration, the STINH stop circuit 13 is
When the MRQOK signal from the OK suppression circuit 14 is changed from OFF to ON, the stage transition suppression stop signal (hereinafter, STINH
Stop signal).

The MRQOK suppression circuit 14 is composed of an inverter 141 and an AND circuit 142. The AND circuit 142 includes the JKFF123 of the MRQOK generation circuit 12.
Invalidation request signals PINV inverted by the MRQOK ₀ signal and the inverter 141 from is inputted, open when invalidation request signal PINV is 0 (off), MRQOK signal is output.

Next, 15 is a stage signal generation circuit, and AND / OR circuit 151, DFF152, AND circuit 153, DFF154, AND circuit 155.
And DFF156.

The AND / OR circuit 151 includes AND circuits 151a and 151b and an OR circuit 151c. The AND circuit 151a receives the MRQOK signal from the MRQOK suppression circuit 14 and the inverted stage transition suppression signal * STINH from the STINH generation circuit 11, and the AND circuit 152b receives the stage transition suppression signal STINH from the STINH generation circuit 11.
And the first stage signal STG1 from the DFF152 is input. The OR circuit 151c receives the respective AND outputs from the AND circuits 151a and 151b.

The DFF152 operates in synchronization with the clock CLK1, the OR output of the OR circuit 151c of the AND / OR circuit 151 is input to its D terminal, and the first stage signal ST is output from its output terminal Q.
G1 is generated.

The AND circuit 153 has Q terminal outputs STG1 and STIN from the DFF152.
The inversion stage transition inhibition signal * STINH from the H generation circuit 11 is input.

The DFF 154 operates in synchronization with the clock CLK1, the AND output of the AND circuit 153 is input to its D terminal, and the second stage signal STG2 is generated from its output terminal Q.

The AND circuit 155 receives the first stage signal STG1 from the DFF152.
And inversion stage transition suppression signal * S from STINH generation circuit 11
TINH is entered.

The DFF 156 operates in synchronization with the clock CLK0, the AND output of the AND circuit 155 is input to its D terminal, and the output terminal Q thereof generates the first stage enable signal STG1V.

Reference numeral 16 is an HITD generation circuit, which includes a DFF 161 and an AND circuit 162.

The DFF161 operates in synchronization with the clock CLK1, the hit signal HIT is input to its D terminal, and its inverted output terminal is an inverted signal of the delayed hit signal HITD delayed by one cycle of the clock CLK1. An inverted delayed hit signal * HITD is generated.

The AND circuit 162 outputs the inverted delay hit signal from the DFF 161 *
The HITD and the first stage valid signal STG1V from the DFF 156 are input, and when the inverted delay hit signal * HITD and the first stage valid signal STG1V are both on, the inverted delay hit signal * HITDV is output.

Reference numeral 17 is a clock suppression generation circuit, which is an inverter 171, A
It is composed of an ND circuit 172 and a JKFF 173.

The AND circuit 171 includes a hit signal * HIT inverted by the inverter 171, an inverted stage transition inhibition signal * STINH from the STINH generation circuit 11, and a first stage signal STG from the DFF152.
1 and are input, and the AND output is input to the J terminal of JKFF173.

The JKFF173 operates in synchronization with the clock CLK0, the K terminal receives the start signal START, and the inverted output terminal * Q thereof outputs the inverted clock inhibition signal * CLKSP which is the inverted signal of the clock inhibition signal CLKSP. It

Reference numeral 18 denotes a clock generation control circuit, which is composed of an AND circuit 181 and controls generation of the clock CLK1. Ie AND
The inverted clock inhibition signal * CLKSP and the clock CLK0 from the JKFF173 of the clock inhibition generation circuit 17 are input to the circuit 181, and when the inverted clock inhibition signal * CLKSP is 1 (on), that is, the clock inhibition signal CLKSP is off. During normal operation, clock CLK0 is output as clock CLK1.

The operation of the memory access control circuit 10 described above will be described in the section for explaining the operation of the next embodiment.

(B) Operation of the Embodiment The operation of the embodiment will be described with reference to the operation timing charts of FIGS. 4 and 5 and the stage transition diagram of FIG.

Also in the embodiment of the present invention, the memory access control of two cycles is performed according to the stage transition shown in FIG. 6, and FIG. 6 is as described above.

First, the memory access control operation common to the above (1) to (3) will be described with reference to the operation timing chart of FIG. In FIG. 4, the clock CLK1 is generated by the clock generation circuit 18 in synchronization with the clock CLK0 (not shown). τ ₁ , τ ₂ etc. indicate each cycle of the clock CLK0 (FIG. 4 (a)). The clock CLK0 is a clock generated in synchronization with the system clock SCLK as described above, and defines the timing of each operation performed in the memory access control circuit 10.

When accessing the main memory (not shown), the processor 26 sends out a memory access request signal MRQ at the memory request stage shown in FIG. 6 (FIG. 4 (b)). Now, in the cycles τ ₁ , τ ₂ and τ ₃ of the clock CLK0, memory access requests are continuously issued.
MRQ is generated, and this is used as memory access request signals MRQ, MRQ and MRQ as shown in FIG. 4 (FIG. 4 (b)).

For the first memory access request signal MRQ issued in tau ₁ cycle, in the same tau ₁ cycle, the memory access request permission signal MR for permitting the memory access request
QOK (indicated by the MRQOK signal) is received and notified to the memory access control circuit (FIG. 4 (c)).

When the DFF152 of the memory access control circuit 10 receives this MRQOK signal, it synchronizes with the clock CLK1 and the next cycle τ
_{At 2} , the first stage signal STG1 (indicated by STG1) is generated and sent to the processor 26 via the control signal bus CB (FIG. 4 (d)).

Upon receiving this first stage signal STG1, the processor
26 performs the first stage processing in the second cycle τ ₂ , sends out the address for accessing the main memory in the address register 251 via the address bus AB (FIG. 4 (f)), and further caches The hit judgment for the memory is performed.

That is, the address sent by the processor 26 first accesses the directory memory 22. If the directory memory 22 has an address corresponding to the address to be accessed, the hit signal HIT becomes 1 to indicate that the cache memory has been hit. If the address corresponding to the accessed address does not exist in the directory memory 22, the hit signal HIT becomes 0, indicating that the cache memory is a mishit.

This hit signal HIT is sent to the memory access control circuit 10 via the MM interface controller 21.

Also, the hit information of the cache memory is the HIT register 2
Stored in 3. The hit information in the HIT register 23 is sent to the cache memory 24, and when the hit signal HIT is 1 (hit the cache memory), the cache memory corresponding to the block number of the directory memory 22 that has hit.
24 areas are selected.

The operation of the embodiment will be described below (1) when the cache memory is hit, (2) when the cache memory is missed, and there is no validation request, and (3)
It will be explained separately when there is a miss in the cache memory and there is an invalidation request.

(1) When the cache memory is hit During normal operation when the cache memory is hit, the memory access control circuit 10 controls the memory access in two cycles.

When the cache memory 24 is hit, that is, when the hit signal HIT is 1, D of the memory access control circuit 10
The FF 154 generates the second stage signal STG2 (indicated by STG1) in the next cycle τ ₃ in synchronization with the clock CLK1 and sends it to the processor 26 (in FIG. 4 (e)).

Upon receiving this first stage signal STG1, the processor
26 performs the second stage processing in the second cycle τ ₃ , reads the data hit in the cache memory 24, and transfers it to the data register 262 via the data bus DB.

On the other hand, in this cycle τ ₃ , the process of the first cycle (first stage) for the next memory access request signal MRQ overlaps with the process of the second cycle (second stage) for the first memory access request signal MRQ. Processing is performed (see STG1 in FIG. 4 (d) and STG2 in (e)).

First cycle of next memory access request signal MRQ (first stage STG1 of τ ₃ cycle in FIG. 4 (d))
When the cache memory 24 is hit at,
_{In four} cycles, the second cycle of the memory access request signal MRQ, that is, the processing of the second stage STG2 is executed.

Similarly, when the cache memory is hit, each process of the first stage STG1 and the second stage STG2 for each memory access request signal MRQ is continuously executed (not shown).

(2) When there is a miss in the cache memory and there is no validation Now, the memory access request signal MRQ performed at τ ₂
In the processing of the first stage STG1 of the above, if the address sent from the processor 26 misses the cache memory 24, the hit signal HIT becomes 0 in the cycle τ ₂ (FIG. 4 (m)), and the HIT register 23 Stored in.

Clock suppression generation circuit 17 of memory access control circuit 10
Is τ ₃ when the hit signal HIT is 0 (miss hit)
In clock cycle, DFF173 clock inhibit signal * CLKSP
(Inverted signal of CLKSP) is generated.

On the other hand, the STINH generation circuit 11 has the hit signal HIT of 0 (miss hit) and the continuous memory access request signal MR.
When the first stage STG1 of Q is on (τ ₃ cycle in FIG. 4 (d)), the stage transition inhibition signal STINH output by JKFF112 is turned on after τ ₄ cycle (FIG. 4 (p)). .

As a result, the value of the first stage signal STG1 of the memory access request signal MRQ generated from the DFF 152 of the memory access control circuit 10 is continuously 1 after the τ ₃ cycle.
(FIG. 4 (d)), the second stage signal STG2 of the memory access request signal MRQ generated from the DFF152 continuously holds the value 1 after τ ₃ cycles ( FIG. 4 (e)).

Further, as described above, when the inverted clock inhibition signal * CLKSP generated by the DFF173 is turned off (the clock inhibition signal CLKSP is turned on) in the τ ₃ cycle, the clock generation circuit 18
Is suppressed from generating the clock CLK1 after τ _{4, and} the control operation of the memory access control circuit 10 after τ ₄ cycle is
It is temporarily suspended (Figs. 4 (r) and (a)).

Due to the mishit to the cache memory 24, while the control operation of the memory access control circuit 10 is temporarily suspended, the MM interface controller 21 reads the mishit data from the main memory (not shown),
While transferring to the processor 26 via the data bus DB, register this read data in the cache memory 24,
A process of registering tag information such as the address in the directory memory 21 is performed. This data transfer process is performed by τ _{4 to} τ ₆
It takes place between cycles.

Data read from the main memory is performed in block units, and a plurality of words (in the figure, D-1 to D in the figure) including the data hit to the memory access request signal MRQ are hit.
-4 word) is read and transferred to the processor 26 and the cache memory 24 (FIG. 4 (g)). When the data of each block is read, the block read signals BLKRD1 ~
BLKRD4 is sent to the memory access control circuit 10, but the block read signal BLKRD2 is shown in FIGS. 4 (h) and (i).
And BLKRD3 are shown.

Processor when the first data D-1 is transferred
Since 26 can move to the next processing, the memory access control circuit 10
The control of the clock CLK may be stopped and its control may be restarted. Therefore, the MM interface controller 21 sets the start signal START to 1 (ON) (τ in FIG. 4 (s)).
₇ ).

JKFF173 of the clock suppression generator circuit 17 has a start signal S
When TART becomes 1, the inverted clock suppression signal * CLKSP is turned on (clock suppression signal CLKSP is turned off) in the next τ ₈ cycle.
To

When the inverted clock suppression signal * CLKSP is turned on, the clock generation circuit 18 synchronizes with the clock CLK0 and the clock CL.
The generation of K1 is restarted (τ _{8 in} FIGS. 4 (a) and 4 (r)).
cycle).

In the present embodiment, in accordance with the gist of the present invention, when there is no invalidation, the time point when the transfer of the mishit data is completed, that is, the time point when the data D-4 is transferred (τ ₁₁
At the end of the cycle), stop stage transition inhibition and start stage transition from the next τ ₁₂ cycle.

That is, when the block read signal BLKRD2 for block 2 becomes 1 (ON) in τ ₉ cycle, MRQOK
The JKFF123 of the generation circuit 12 changes the MRQOK signal from 0 to 1 (off to on). Since the invalidation request signal PINV is 0 when there is no invalidation request, the MRQOK suppression circuit 14 outputs the MRQOK signal from the JKFF123 as it is without turning off the MRQOK signal and turns it from off to on (fourth). (Τ ₁₀ cycle in figure (b)).

The STINH stop circuit 13 detects that the MRQOK signal from the MRQOK suppress circuit 14 has changed from OFF to ON, generates a STINH stop signal, and inputs it to the K terminal of JKFF112.

Upon receiving this STINH stop signal, the STINH generation circuit 112 turns off the stage transition inhibition signal STINH (* STINH is on) (τ ₁₁ cycle in FIG. 4 (p)).

As a result, the first stage STG1, which is a stage process related to the memory access request signal MRQ, continues to remain in the ON state until τ ₁₁ cycles, and the hit determination for the cache memory 24 becomes possible, and a valid hit determination is performed at τ _11. , Τ ₁₂ cycle, the second stage STG2 is normally executed (FIG. 4, (d), (e), (m)).

In the τ ₁₂ cycle, similar to the case of the τ ₃ cycle described above, the second cycle processing (second stage STG2) for the memory access request signal MRQ and the first cycle processing (first stage) for the next memory access request signal MRQ (first Stage STG
And 1) are performed in parallel (Figs. 4 (d), (e),
(M), (n)).

As described above, when there is a miss in the cache memory and there is no validation request, each stage that was immediately interrupted from the next τ ₁₂ cycle after the τ ₁₁ cycle in which the data transfer for the miss hit data was completed. The process is restarted.

(3) When there is a miss in the cache memory and there is an invalidation request Memory access control when there is a miss in the cache memory and there is an invalidation request will be described with reference to FIG.

FIG. 5 shows the same operation timing chart as FIG. 4, and the meaning of each symbol of (a) CLK to (s) START and the operation contents up to τ ₉ cycle are the same as those of FIG. Is the same.

Further, (k) INVL is an invalidation signal for invalidating the data registered in the cache memory 24, as described above, and upon receipt of this invalidation signal, the invalidation signal in the directory memory 22 is invalidated. An invalid flag (not shown) is set in the area corresponding to the target data area.

If the memory access request signal MRQ is written to the main memory area registered in the directory memory 22 of its own cache memory 24 by the other processor or DMA before τ ₁₁ cycles, it is assumed. The monitoring directory 211 generates an invalidation request signal PINVL in the τ ₁₀ cycle, which is one cycle before the τ ₁₁ cycle in which the data transfer is completed, and sends it to the memory access control circuit 10.

Since the invalidation request must always be given priority over the stage processing, the MR of the memory access control circuit 10
When the invalidation request signal PINVL becomes 1 (on), the QOK suppression circuit 14 cuts off the MRQOK signal from the MRQOK generation circuit 12 and holds the 0 (off) state (FIG. 4 (c)).
Τ ₁₀ cycles).

Therefore, the STINH stop circuit 13 does not generate the STINH stop signal. The STINH generation circuit 11 continues to generate the stage transition suppression signal STINH even in the τ ₁₀ cycle to suppress the stage transition.

When there is only one invalidation request, the MRQOK suppression circuit 14 receives the MRQO from the MRQOK generation circuit 12 in the τ ₁₁ cycle when the invalidation request PINVL is turned off.
The suppression of the K signal is stopped, the MRQOK signal is generated, and the signal is turned from off to on (τ ₁₁ cycle in FIG. 4 (b)).

STINH stop circuit 13 receives MRQOK from MRQOK suppress circuit 14.
Detecting that the signal has changed from off to on, generate a STINH stop signal and input it to the K terminal of JKFF112.

Upon receiving this STINH stop signal, the STINH circuit 11 turns off the stage transition inhibition signal STINH (* STINH is on) (τ ₁₂ cycle in FIG. 4 (p)).

As a result, the first stage STG1, which is a stage process related to the memory access request signal MRQ, remains on for up to τ ₁₂ cycles, and a valid hit determination is performed at τ _12, which enables the hit determination to the cache memory 24. , Τ ₁₃ cycles, the second stage STG2 is normally executed (FIG. 4, (d), (e), (m)).

On the other hand, in τ ₁₁ cycle, the directory memory
For 21, the invalidation processing is performed on the invalidation target data (τ ₁₁ cycle in FIG. 4 (k)).

If a plurality of validation requests occur consecutively following the validation request in τ ₁₀ cycle, the MRQOK suppression circuit 14 suppresses the generation of the MRQOK signal and the STINH circuit 11 suppresses the stage transition for that period. Continue to generate signal STINH.

In the cycle in which the invalidation request PINVL is turned off, the MRQOK suppression circuit 14 stops the suppression of the MRQOK signal, and in response to this, the STINH circuit 11 turns off the stage transition suppression signal STINH (* STINH is on). .

As a result, in the same manner as described above, the processing of each temporarily suspended stage is continued normally.

As described above, only when there is a miss hit in the cache memory and there is an invalidation request, one cycle is opened next to the cycle in which the data transfer for the miss hit data is completed, and the invalidation processing is performed. Then, from the next cycle, each stage processing which has been interrupted immediately is restarted.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various modifications in accordance with the gist of the invention are possible.

For example, the data transfer amount in the case of a mishit in the cache memory is not limited to 4 words. In addition, the present invention can be applied even when a plurality of validation requests at the time of a miss hit are consecutive,
This is as described above in the embodiment.

(Effect)

As described above, according to the present invention, the following effects can be obtained.

(1) At the time of a miss hit in the cache memory, the stage processing is restarted with a delay of one cycle after the end of the data transfer of the miss hit data only when an invalidation request occurs, so it is useless when there is no invalidation request. The cycle is eliminated, and the memory access processing efficiency can be improved.

(2) If the stage processing is restarted with a delay of the number of cycles corresponding to the number of invalidation requests, even if invalidation requests are continuously generated, these invalidation processing can be normally processed and interrupted. It is possible to normally resume the stage processing for each access request made.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention, FIG. 2 is an explanatory diagram of a memory access control system in which a memory access control circuit according to an embodiment of the present invention is used, and FIG. FIG. 4 is an explanatory diagram of the configuration of an example, FIG. 4 is an explanatory diagram of an operation timing chart of the same embodiment, and FIG. 5 is an explanatory diagram of an operation timing chart of the same embodiment when there is a miss and there is an invalidation. FIG. 7 is an explanatory diagram of stage transition, FIG. 7 is an explanatory diagram of a conventional memory access control system, FIG. 8 is an explanatory diagram of an operation timing chart of the conventional memory access control system, and FIG. 9 is a conventional memory access control system. Explanatory diagram of the operation timing chart at the time of a mishit in and also when there is invalidation. 1 and 2, 10 ... Memory access control circuit, 11 ... Stage transition suppression generation circuit (STINH generation circuit), 12 ... Memory access request permission signal generation circuit (MRQOK generation circuit), 13 ... Stage transition suppression circuit (STINH stop circuit), 14 ... Memory access request permission suppression circuit (MRQOK suppression circuit).

Front Page Continuation (72) Kenji Hoshi, Inventor Kenji Hoshiodachu, Nakahara-ku, Kawasaki-shi, Kanagawa 1015, Fujitsu Limited (72) Inventor Eiji Kanaya 1015, Uedotachu, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (56) Reference References JP 61-165154 (JP, A) JP 61-221845 (JP, A) JP 63-214849 (JP, A) JP 3-271843 (JP, A) JP 2- 90265 (JP, A)

Claims (3)

(57) [Claims] 1. An address is sent in the first cycle, data is transferred in the second cycle by overlapping with the first cycle of the next access, and the directory memory is accessed by the address sent in the first cycle and the address. When the hit information and the address information obtained by the above are held for the second cycle, and the hit information indicates a hit, the cache memory is accessed by the held address information in the second cycle, and a miss hit occurs. Block data read from the main memory according to the address information, and when the hit information output in the first cycle of access indicates a mishit, block the clock generation and read from the main memory according to the address information. Clock suppression signal that stops suppression when the first data of In a memory access control circuit that includes a raw circuit and that accesses a cache memory in two cycles, the hit information output in the first cycle indicates a mishit, and the stage of the first cycle of continuous access is ON. A stage transition inhibition signal generation circuit (11) that generates a stage transition inhibition signal that inhibits the stage transition of the second cycle of the first access that had indicated the above-mentioned mishit, and a memory access request permission signal at the time of mishit And a memory access request permission signal generation circuit (12) for turning on the memory access request permission signal in the cycle immediately before the last data read from the main memory by the address information reaches the cache memory.
And a stage transition inhibition stop circuit (13) that detects that the memory access request permission signal is turned from off to on and stops the stage transition inhibition signal generated by the transition inhibition signal generation circuit (11). A memory access control circuit characterized by the above. 2. In the cycle for turning on the memory access request permission signal, when an invalidation request for the self cache memory is made, the memory access request permission signal is turned on for performing invalidation processing in the cycle. Memory access request permission suppression circuit (1
4. The memory access control circuit according to claim 1, further comprising: 4). 3. An access request permission suppression circuit (14), in the cycle of turning on the memory access request permission signal, if invalidation requests of its own cache memory are continuously issued, memory access continues during that period. 3. The memory access control circuit according to claim 2, wherein the request permission signal is suppressed, and the memory access request permission signal is turned on from a cycle in which invalidation is no longer required.