JPH0721133A - Information processor - Google Patents

Abstract

PURPOSE:To improve the reliability of a system by eliminating a contradiction due to a data discrepant with a main storage device if a cache is hit in test- and-set mode. CONSTITUTION:A main storage controller 14 is provided with a start signal generating circuit 12 which delays a start indication to a CPU 10 by a specific time and a processor 3 accesses a semaphore bit setting part by test-and-set operation; when the cache memory 11 is hit, the start indication is delayed and after the corresponding bit of the cache memory 11 is made ineffective, the start indication is sent to the processor. In this case, the start indication from the main storage device 14 is delayed behind a start indication at other read time only when the storage device is accessed by the test-and-set operation or only when the cache memory 11 is hit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which a plurality of processing devices connected via a memory bus use a common main memory device, and more particularly, to a test and semaphore bit test of the main memory device. The present invention relates to an information processing apparatus including a cache memory control mechanism that controls invalidation of a cache memory when accessed by a set instruction.

[0002]

2. Description of the Related Art FIGS. 10 to 13 are views showing conventional examples. In FIGS. 10 to 13, 1 is a main storage device, 2 is a semaphore area, 3 is a processing device (processor), Four
Is a memory bus, 5 is a memory bus monitoring unit, 6 is a memory bus access control unit, 7 is a data receiving unit, 8 is a request control unit, 9 is a cache memory control unit, 10 is a CPU (central processing unit), and 11 is a cache. Memory, 12 is a start signal generation circuit, 13 is a cache invalidation signal generation circuit, 15, 17, 18 and 19 are AND circuits, 16 and 2
Reference numerals 0 and 21 denote OR circuits.

In the following description, the "signal present" state is described as a high level "1" and the "no signal" state is described as a low level "0". §1: Explanation of system configuration ... FIG. 10, FIG. 11, FIG.
See FIG. 2. FIG. 10 is a block diagram of a conventional system (information processing apparatus), FIG.
1 is a block diagram of the processing apparatus of FIG. 10, and FIG. 12 is a partial detailed view of FIG.

Conventionally, as shown in FIG. 10, a plurality of processing units (0, 1, ...) Connected via a memory bus 4.
n), a system (information processing device) using a common main storage device 1 has been known.

In such a system, the main storage device 1 is provided with a common area (hereinafter referred to as "semaphore area") 2 having a mutual exclusion control information (hereinafter referred to as "semaphore bit") setting section for each storage area. There is. Further, each processing device 3 has the configuration shown in FIG. 11, for example.

That is, each processing device 3 is provided with a main memory control device 14, a CPU 10, a cache memory 11, etc., and the main memory control device 14 has a memory bus monitoring unit 5, a memory bus access control unit 6, and the like. A data receiving unit 7, a request control unit 8, a cache memory control unit 9 and the like are provided.

Further, the request control section 8 is provided with a start signal generation circuit 12, and the cache memory control section 9 is provided with a cache invalidation signal generation circuit 13.

The start signal generating circuit 12 is shown in FIG.
As shown in (A), it is composed of an AND circuit 15 and an OR circuit 16. Further, the cache invalidation signal generation circuit 13 has the AND circuit 1 as shown in FIG.
7, 18 and 19 and OR circuits 20 and 21.

The start signal generation circuit 12 has
The signals S1 to S3 are input, and a start signal (START) is generated from these input signals and output. Also,
The cache invalidation signal generation circuit 13 includes S3 and S1.
Each signal of S1, S13, S14, S15, and S16 is input, and a cache invalidation signal (Voff) is generated and output.

§2: Description of the operation of the start signal generation circuit ... See FIG. 12A. The start signal generation circuit 12 includes S1, S2, and S3.
In this case, S1 is a data transfer timing signal of the stage 2 by its own device (see S which will be described later).
Signal on the memory bus in TAGE2), S2 is a read access signal (a signal output from the CPU 10), S3 is a test and set (TS) signal (CPU1)
Signal output from 0).

In this circuit, when the signal of S1 is present (high level "1" state) and the signal of S2 or S3 is present (high level "1" state), the start signal (ST
ART) is output (the high level "1" is set).

§3: Description of operation of cashier invalidation signal generation circuit ... See FIG. 12B. The cashier invalidation signal generation circuit includes S3, S11, and S.
The signals of 13, S14, S15, and S16 are input.

In this case, S11 is a data transfer timing signal of the stage 3 by its own device (STAGE3 which will be described later).
Signal on the memory bus in S.), S13 is a data transfer timing signal of the stage 3 by another processing device (a signal on the memory bus in STAGE 3 described later), S14.
Is a write access signal (a signal on the memory bus) by another processing device, S15 is a signal of a test and set instruction by another processing device, and S16 is a cache hit signal.

In this circuit, the cache invalidation signal Vof
f is output (high level “1” state) in the following cases. : When the signals S11 and S3 are present (high level "1" state) and the signal S16 is present (high level "1" state), the cache invalidation signal Voff is output.

When the signals S13 and S16 are present (high level "1" state) and the signals S14 or S15 are present (high level "1" state), the cache invalidation signal Voff is output. To be done.

As described above, the cache invalidation signal V
When off is output, the cache memory control unit 9 invalidates the cache memory 11 (invalidates the corresponding block).

§4: Processing Description of Processing Device--See FIG. 13 FIG. 13 is a conventional processing explanatory view (time chart at the time of cache hit in test and set).

Conventionally, when the CPU 10 in the processing device 3 performs a read (external read) to the main storage device 1,
The CPU 10 does not proceed to the next operation until the read data arrives, and when the read data arrives, the CPU 10 receives a start instruction (instruction based on the start signal) from the request control unit 8 of the main memory control device 14 and operates. Resume.

This also applies to the test and set by the CPU 10. Here, the “test and set” is an instruction (access instruction to the mutual exclusion control information setting unit) of issuing an address, reading data, and writing data during one acquisition of the memory bus. is there.

In the case of test and set, when the cache memory 11 hits, a data mismatch with the main memory 1 occurs, so it is necessary to invalidate the cache memory 11.

FIG. 13 shows an example of a timing chart in the case where the self-processing device 3 performs a test and set and the cache memory is hit. First, the address is output in stage 1, and the data is read in stage 2. Then, in this stage 2, a start signal is issued and the CPU restarts the operation.

Then, in stage 3, the cache invalidation signal generation circuit 13 outputs the cache invalidation signal Voff.
Is output, and the corresponding block of the cache memory 11 is invalidated in the stage 3.

In this way, the cache memory is invalidated due to the test and set hit after the start instruction by the test and set.

[0024]

SUMMARY OF THE INVENTION The above-mentioned conventional devices have the following problems. Conventionally, the cache memory is invalidated (stage 3) due to the cache hit of the test and set after the test and set start instruction (stage 2) by the self-processing device.

When the CPU receives a start instruction from the main storage controller, it resumes operation. If there is a read access to the same block as the test and set immediately after the test and set, it means that the cache memory has not been invalidated. The old data with different contents will be read, resulting in inconsistency.

The present invention solves such a conventional problem and eliminates a contradiction caused by a data mismatch with the main memory when a cache hit occurs during test and set.
The purpose is to improve the reliability of the system.

[0027]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the same parts as those in FIGS. 10 to 13 are designated by the same reference numerals. Reference numeral 27 indicates a delay circuit.

The present invention has the following structure to solve the above problems. (A): to the common main memory device 1 via the memory bus 4,
A plurality of processing devices 3 are connected, a cache memory 11 and a main storage control device 14 are provided in each processing device 3, and a mutual exclusion control information (semaphore bit) setting unit is provided in the main storage device 1 for each storage area. In addition to providing the common area (semaphore area 2) that the processing apparatus 3 has, when the processing device 3 accesses the mutual exclusion control information setting unit by an access command (test and set) to the mutual exclusion control information setting unit,
A function to invalidate the block of the cache memory when the cache memory 11 is hit, and: When the external read is performed, the operation is stopped until the read data arrives, and when the read data arrives, the main storage control device 14
In the information processing apparatus having the function of restarting the operation in response to the start instruction from, the main memory control device 14 is provided with delay means (start signal generation circuit 12 having the delay circuit 27) for delaying the start instruction by a predetermined time, and processing is performed. When the device 3 accesses the mutual exclusion control information setting unit of the main storage device 1 by an access instruction (test and set) to the mutual exclusion control information setting unit and the cache memory 11 hits, the delay unit The information processing apparatus that allows the start instruction to be issued to the self-processing apparatus after the relevant block of the cache memory 11 is invalidated by delaying the start instruction.

(B): In the configuration (a), the processing device 3
However, only when the mutual exclusion control information setting unit of the main storage device 1 is accessed by an access command (test and set) to the mutual exclusion control information setting unit, the start instruction from the main storage control device 14, An information processing device that delays the start instruction for other external reads.

(C): In the configuration (a), the processing device 3
Is accessed by the access instruction (test and set) to the mutual exclusion control information setting unit of the main storage device 1, the cache memory 1
An information processing apparatus that delays a start instruction from the main memory control device 14 only when 1 is hit, compared to other start instructions for external read.

[0031]

The operation of the present invention based on the above configuration will be described with reference to FIG. When the CPU 10 in the processing device 3 performs an external read (read other than the self processing device) to the main storage device 1, the CPU 10 does not proceed to the next operation until the read data arrives, and the read data is read. When the data arrives, the main memory control device 14 receives a start instruction to restart the operation.

This also applies to the case of an access command (test and set) to the mutual exclusion control information setting section by the CPU 10. In the case of this instruction, when the cache memory 11 hits, a data mismatch with the main storage device 1 occurs, so it is necessary to invalidate the cache memory 11.

In the processing device 3, first, the CPU 10 outputs an address and reads data. Thereafter, when a start instruction (instruction based on the output signal of the start signal generation circuit 12) is issued from the main memory control device 14, the CPU 10 restarts the operation. In this case, each processing device 3 performs the following control.

(1): The processing device 3 accesses the mutual exclusion control information (semaphore bit) setting unit of the main storage device 1 by an access command (test and set) to the mutual exclusion control information setting unit, The cache memory 11
When is hit, the delay circuit 27 delays the start instruction to invalidate the block in the cache memory 11 and then control the self-processing apparatus to issue the start instruction.

(2): Main memory only when the processor 3 accesses the mutual exclusion control information setting unit of the main memory 1 by an access command (test and set) to the mutual exclusion control information setting unit The delay circuit 27 controls the start instruction from the control device 14 so as to be delayed from the start instruction at the time of another external read.

(3): When the processor 3 accesses the mutual exclusion control information setting unit of the main memory 1 by an access command (test and set) to the mutual exclusion control information setting unit, the cache memory 11 thereof is Only when a hit is made, the start instruction from the main memory control device 14 is controlled by the delay circuit 27 so as to be delayed from the start instruction at the time of another external read.

As described above, even if the cache memory is hit by the test and set of the own processing device and immediately after that, there is a read access to the same block as the test and set, the old data before invalidation Can be prevented from leading.

Further, in the case of a cache miss hit at the time of test and set by the own processing device, it is not necessary to invalidate the cache. Therefore, in this case, it is not necessary to delay the start timing.

Therefore, as described in (3) above, if the start timing is delayed only when the test and set by the own processing device is a cache hit, useless waiting time is eliminated.

In this way, when the cache memory is hit during the test and set, the contradiction caused by the data mismatch with the main storage device can be resolved, and the reliability of the system can be improved.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 9 are views showing an embodiment. In FIGS. 2 to 9, the same parts as those in FIGS. 1 and 10 to 13 are designated by the same reference numerals. Also, 24, 25, 29, 30, 31
Is an AND circuit, 26 and 32 are OR circuits, 28 is a D-FF
(Delayed flip-flop) is shown.

(Description Common to Each Embodiment) FIG. 2 is a system configuration diagram of the embodiment, and FIG. 3 is a detailed configuration diagram of a processing device. First, a description common to each embodiment will be given based on FIGS. 2 and 3.

As shown in FIG. 2, the system of this embodiment uses a main storage device 1 in which a plurality of processing devices (0, 1, ... N) connected via a memory bus 4 are common. System (information processing device).

Then, in the main storage device 1, semaphore bits (mutual exclusion control information) are set (set a value of 1/0) for each area (area 1, area 2, ... Area n). There is provided a semaphore area (common area) 2 having a mutual exclusion control information setting unit for.

Further, each processing device 3 is provided with a main memory control device 14, a CPU 10, a cache memory 11 and the like. Further, the main memory control device 14 is provided with a memory bus monitoring unit 5, a memory bus access control unit 6, a data receiving unit 7, a request control unit 8, a cache memory control unit 9, and the like.

As in the conventional example, the request control unit 8 is provided with a start signal generation circuit 12, and the cache memory control unit 9 is provided with a cache invalidation signal generation circuit 13 ( The same as FIG. 11) is omitted in the drawing.

In this case, the cache invalidation signal generation circuit 13 has the same configuration as that shown in FIG. 12B, so that illustration and description thereof will be omitted in each of the following embodiments. (Explanation of the First Embodiment) FIG. 4 is a diagram showing a start signal generating circuit of the first embodiment, and FIG. 5 is a process explanatory diagram of the first embodiment.
(Time chart at the time of read access), FIG. 6 is a process explanatory diagram 2 (time chart at the time of test and set) of the first embodiment.

§1: Description of Start Signal Generating Circuit--See FIG. 4 In the first embodiment, the circuit having the configuration shown in FIG. 4 is used as the start signal generating circuit.

This circuit includes AND circuits 24 and 25 and an O circuit.
It is composed of an R circuit 26 and a delay circuit 27. The delay circuit 27 is composed of a plurality of D-FFs (delay flip-flops) 28 (in this example, three D-Fs).
A system clock is supplied to the D-FF.

The start signal generating circuit 12 has an S
The signals of 1, S2, and S3 are input, but in this case, S1
Is a data transfer timing signal (STAG
E2 is a signal on the memory bus), S2 is a read access signal (a signal output from the CPU 10), and S3 is a test and set signal (a signal output from the CPU 10) (the same as the signal in FIG. 12).

The AND circuit 24 receives the signals S1 and S2, and the AND circuit 25 receives the signals S1 and S3. The delay circuit 27 includes an AND circuit 25.
Of the AND circuit 2 is input to the OR circuit 26.
4 and the output signal of the delay circuit 27 are input.

In this circuit, when the signals S1 and S2 are present (state of high level "1"), the OR circuit 2 is immediately activated.
A start signal (START) is output from 6, but S
When there is a signal of 1, S3 (state of high level "1")
Does not immediately output the start signal (START).

That is, when the signals of S1 and S3 are input, the output of the AND circuit 25 immediately becomes the high level "1", but this high level signal is delayed by the delay circuit 27.
It is input to the OR circuit 26 after being delayed for a predetermined time.

Therefore, after the signals of S1 and S3 are input,
The OR circuit 26 outputs the start signal (START) after a delay of a predetermined time (3 cycles). §2: Description of processing at read access ... See FIG. 5 At the time of read access, first, stage 1 (STAGE
The address is output in 1) and the data is read in stage 2 (STAGE2).

At this time, the signals S1 and S2 shown in FIG. 4 both become high level "1". Therefore, stage 2
Then, the start signal (START) is output, and the CPU1
0 restarts the process.

That is, the start timing at the read access is the read data arrival timing (STAGE2) as in the conventional example. §3: Processing explanation at the time of test and set ... See FIG. 6 The processing when the cache memory is hit in the test and set is as follows. Start timing at test and set (timing to restart CPU processing)
Is a timing obtained by delaying the read data arrival timing.

Here, the delay cycle is 3 cycles, but the delay amount may be arbitrary as long as the start timing at the test and set is later than the invalidation timing of the cache memory.

As shown in FIG. 6, first, an address is issued in stage 1 and data is read in stage 2. After that, the cache memory is invalidated in stage 3 (this point is the same as the conventional example shown in FIG. 13).

In the stage 2 which has read the data, the signals S1 and S3 in FIG. 4 are at high level "1" and the output of the AND circuit 25 is at high level "1". The delay circuit 27 delays the signal by a predetermined time (3 cycles) and outputs it from the OR circuit 26. Therefore, the start signal is output with a delay of 3 cycles.

Therefore, after the cache memory is invalidated, a start signal can be issued to restart the processing of the CPU 10. Therefore, according to the first embodiment, even if the test and set of the own processing device has a cache hit and immediately after that there is a read access to the same block as the test and set, the old data before invalidation is read. There is nothing to do.

(Explanation of the Second Embodiment) FIG. 7 is a diagram showing a start signal generation circuit of the second embodiment, and FIG. 8 is an explanation of the processing of the second embodiment. FIG. 1 (at the time of a cache miss in the test and set). 9 is a process explanatory diagram 2 of the second embodiment (a time chart at the time of a cache hit in the test and set).

§1: Description of Start Signal Generating Circuit--See FIG. 7 In the second embodiment, the circuit having the configuration shown in FIG. 7 is used as the start signal generating circuit. This circuit is AND circuit 2
It is composed of 9, 30, 31, an OR circuit 32, and a delay circuit 27.

The delay circuit 27 includes a plurality (two in this example) of D-FFs (delay type flip-flops) 2.
8 (in this example, two D-FFs delay two cycles). Then, a system clock is supplied to the D-FF.

The start signal generating circuit 12 has an S
The signals of 1, S2, S3, S11, and S16 are input.
S1 is a data transfer timing signal by the device itself (a signal on the memory bus in STAGE2), S2 is a read access signal (a signal output from the CPU 10), S3
Is a test and set signal (a signal output from the CPU 10), S11 is a data transfer timing signal by the device itself (a signal on a memory bus in STAGE 3 described later), and S16 is a cache hit signal.

In this case, the AND circuit 29 has S1, S
The signal of 2 is input, and the signals of S11, S3, and S16 are input to the AND circuit 30 and the AND circuit 31. However, A
The signal of S16 is inverted and input to the ND circuit 30.

The delay circuit 27 includes an AND circuit 31.
Of the AND circuit 2 is input to the OR circuit 32.
The output signals of 9 and 30 and the output signal of the delay circuit 27 are input.

In this circuit, when the signals S1 and S2 are present (high level "1" state), and the signals S11 and S3 are present (high level "1" state), and the signal S16 is present. When there is no (low level “0” state), immediately O
A start signal (START) is output from the R circuit 32.

However, when the signals of S11, S3 and S16 are present (all are at the high level "1"), the AND circuit 3
The output of 1 immediately becomes a high level "1", but this signal is input to the OR circuit 32 with a delay of a predetermined time in the delay circuit 27 (two cycles delayed in this example).

Therefore, after the signals of S11, S3 and S16 are input, the start signal (START) is output from the OR circuit 32 with a delay of a predetermined time (2 cycles). §2: Process explanation at the time of test and set ... See FIGS. 8 and 9. FIG. 8 is a process explanation of the second embodiment. FIG. 1 (when a cache miss hits in the test and set), FIG. 9 shows the second embodiment. Processing explanation figure 2 (when cache hits in test and set)
Is.

In the second embodiment, the start timing at the read access and the start timing at the cache hit in the test and set are the same as those in the first embodiment.

However, it is not necessary to invalidate the cache memory in the case of a cache miss hit during the test and set by the own processing device. So in this case,
There is no need to delay the start timing. Therefore,
In the second embodiment, the processing is performed as follows.

When the cache memory is a mishit in the test and set, the following processing is performed. The start timing in this case is as shown in FIG. That is, the address is issued in stage 1, the data is read in stage 2, and the read data arrives. Then, in stage 3, the cache hit is judged and the cache mishit is found.

Therefore, in stage 3, S shown in FIG.
The signal 11 is high level "1", the signal S3 is high level "1", the signal S16 is low level "0" (cache miss), and the output of the AND circuit 30 is high level "1".

As a result, in the stage 3, the start signal (START) is output from the OR circuit 32, and the CPU 10
Restarts processing (does not delay the start signal). : If the cache memory hits in the test and set, the process is as follows.

The start timing in this case is as shown in FIG. First, an address is issued in stage 1 and data is read in stage 2, but cache hit determination is performed in stage 3.

If a cache hit is determined in this determination, the cache memory is invalidated in stage 3. Further, in stage 3, the signal of S11 shown in FIG. 7 becomes the high level "1", the signal of S3 becomes the high level "1", and the signal of S16 becomes the high level "1".
The output of the AND circuit 31 becomes high level "1".

This high-level signal is delayed by the delay circuit 27 for a predetermined time (two cycles in this example) and output to the OR circuit 32. As a result, the OR circuit 32 delays the start signal (STAR) by two cycles after the stage 3.
T) is output.

As described above, in the second embodiment, the start timing is delayed only when the test and set by the own processing device is a cache hit (in the first embodiment, the test and set by the own device is delayed. Even if the set does not hit the cache, the start timing is delayed.) Therefore, there is no unnecessary waiting time.

[0079]

As described above, the present invention has the following effects. : The start timing at the time of test and set of its own device (processing device) is delayed as compared with that at the time of other read access as necessary.

Therefore, it is possible to eliminate the contradiction caused by the data mismatch with the main memory when a cache hit occurs in the test and set. In the second embodiment, since the start timing is delayed only when the test and set by the own processing device is a cache hit, unnecessary waiting time is eliminated and the processing speed is increased.

By the above, system reliability is improved and high-speed processing is possible.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of an embodiment.

FIG. 3 is a detailed configuration diagram of a processing device.

FIG. 4 is a diagram showing a start signal generation circuit of the first embodiment.

FIG. 5 is a process explanatory diagram 1 (time chart at the time of read access) of the first embodiment.

FIG. 6 is a process explanatory diagram 2 (time chart during test and set) of the first embodiment.

FIG. 7 is a start signal generation circuit according to a second embodiment.

FIG. 8 is a process explanatory diagram 1 of the second embodiment (a time chart at the time of a cache miss hit in the test and set).

FIG. 9 is a process explanatory diagram 2 of the second embodiment (a time chart at the time of a cache hit in the test and set).

FIG. 10 is a conventional system configuration diagram.

11 is a configuration diagram of the processing apparatus of FIG.

FIG. 12 is a partial detailed view of FIG. 11.

FIG. 13 is an explanatory diagram of a conventional process (time chart when a cache hit occurs in test and set).

[Explanation of symbols]

 1 Main Storage Device 2 Semaphore Area (Common Area) 3 Processing Device 4 Memory Bus 10 CPU (Central Processing Unit) 11 Cache Memory 12 Start Signal Generation Circuit 14 Main Storage Control Device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Odawara 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Nonaka 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Kenji Hoshi, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited

Claims (3)

[Claims] 1. A plurality of processing devices (3) are connected to a common main memory device (1) via a memory bus (4), and each processing device (3) includes a cache memory (11) and a main memory. A storage controller (14) is provided, and a common area (semaphore area) (2) having a mutual exclusion control information (semaphore bit) setting unit for each storage area is provided in the main memory (1). (3): When the cache memory (11) is hit when the mutual exclusion control information setting unit is accessed by an access command (test and set) to the mutual exclusion control information setting unit, Function to invalidate block: When external read, operation is stopped until read data arrives, and when read data arrives, start instruction from main storage controller (14) In an information processing apparatus having a function of resuming operation, a delay unit (12, 27) for delaying the start instruction by a predetermined time is provided in the main storage control device (14), and the processing device (3) is a main storage device. When the cache memory (11) is accessed by accessing the mutual exclusion control information setting unit (1) by an access instruction (test and set) to the mutual exclusion control information setting unit, the delay unit starts the instruction. The information processing apparatus is characterized in that the start instruction can be issued to the self-processing apparatus after the block in the cache memory (11) is invalidated by delaying. 2. Only when the processing device (3) accesses the mutual exclusion control information setting unit of the main storage device (1) by an access command (test and set) to the mutual exclusion control information setting unit. 2. The information processing apparatus according to claim 1, wherein the start instruction from the main storage control device (14) is delayed from the start instruction at the time of another external read. 3. A cache memory when the processing device (3) accesses the mutual exclusion control information setting unit of the main storage device (1) by an access instruction (test and set) to the mutual exclusion control information setting unit. The information processing apparatus according to claim 1, wherein the start instruction from the main memory control device (14) is delayed from the start instruction at the time of another external read only when (11) is hit.