JP6398449B2 - Electronic information recording medium, processor module operation control method, and processor module operation control program - Google Patents

Description

  The present invention relates to a technical field of an electronic information recording medium including a plurality of processor modules.

  Conventionally, in IC cards, internal confidential information may be illegally leaked due to a failure use attack using a laser beam or the like, and countermeasures such as detecting an abnormality have been studied (for example, Patent Document 1). And Patent Document 2). In general, the process for detecting an abnormality is redundant, and if this is performed, the processing time is longer than that originally required from the outside. Although it is possible to prepare a dedicated circuit for detecting fraud, for example, when the check code is calculated for the program code being executed, the check code calculation method is fixed or selective. If a fatal defect is found in this calculation method, it is difficult to cope with it.

  By the way, there is known a multiprocessor system in which a plurality of processor modules each including a cache memory are connected to a split-type bus and each processor module shares a memory (see, for example, Patent Document 3).

Japanese Patent No. 5200664 Japanese Patent No. 4976854 Japanese Patent No. 3219422

  As in the multiprocessor system disclosed in Patent Document 3, an IC card including a plurality of processor modules and performing processing for a request from the outside of a part of the processor modules is assumed. In such an IC card, each processor module can function independently, but the memory size of the cache memory included in the processor module is limited to about several kilobytes. For this reason, when the program code or data does not exist in the cache memory, a cache miss occurs, and data transfer (memory transfer) from the memory to the cache memory via the bus is required. In the interlock-type bus, the bus is occupied by one processor module during the memory transfer, but the other processor module also waits until the memory transfer is completed when a cache miss occurs. Must-have. On the other hand, even in the case of a split type bus, the bus is occupied by one processor module for a time divided at a predetermined interval. For this reason, these waiting times may become a fatal problem in processing that requires high speed such as communication. In addition, when an abnormality is detected, there is a possibility that an illegal situation spreads by proceeding with normal processing.

  Accordingly, the present invention has been made in view of the above problems and the like, and an electronic information recording medium and processor capable of preferentially operating any one of a plurality of processor modules depending on the situation. It is an object to provide a module operation control method and a processor module operation control program.

In order to solve the above-described problem, the invention described in claim 1 includes a storage unit for storing program code or data, and a plurality of caches for a part of the program code or data acquired from the storage unit via a bus. An electronic information recording medium comprising a plurality of processor modules that perform different processes according to roles, and is stopped when a cache miss of the program code or data occurs among the plurality of processor modules In a plurality of processor modules including a setting unit that presets the processor module, a determination unit that determines whether or not the cache miss has occurred, and the processor module that is preset by the setting unit by the determination unit the cache miss is issued If it is determined the a, stops the preset operation of the processor module by said setting means, an act of the processor module other than said processor module being the stop, from the storage unit, are the stops Control means for performing an operation of acquiring the program code or data subject to the cache miss in the processor module other than the processor module .

The invention according to claim 2 is a storage means for storing program code or data, and a plurality of processor modules for caching a part of the program code or data acquired from the storage means via a bus. An operation control method for the processor module in an electronic information recording medium comprising a plurality of processor modules that execute different processes depending on the program code or data when a cache miss occurs in the program code or data . a setting step for setting beforehand the processor module, wherein the cache and determining whether or not a cache miss occurs, in a plurality of processor modules including the processor module is set in advance by the setting step If the scan is determined in said determining step to have occurred, the setting stops the preset operation of the processor module in step, an act of the processor module other than said processor modules such suspension, the An operation of acquiring the program code or data subject to the cache miss in the processor module other than the processor module to be stopped is performed from a storage unit .

The invention according to claim 3 is a storage means for storing program code or data, and a plurality of processor modules for caching a part of the program code or data acquired from the storage means via a bus. A setting for presetting the processor module to be stopped when a cache miss of the program code or data occurs in a computer in an electronic information recording medium including a plurality of processor modules that execute different processes depending on steps and, wherein the determination step and a cache miss and determining whether or not generated, the cache miss in a plurality of processor modules including the processor module is set in advance by the setting step occurs If it is determined, the set is stopped a preset operation of the processor module in step, an act of the processor module other than said processor module being the stop, from the storage means is the stop the Performing an operation of acquiring the program code or data that is the target of the cache miss in the processor module other than the processor module .

  According to the present invention, one of the plurality of processor modules can be preferentially operated according to the situation.

2 is a diagram showing an example of a schematic configuration of an IC chip C. FIG. 3 is a diagram illustrating a configuration example of a special function register in Embodiment 1. FIG. 3 is a flowchart illustrating an example of processing performed by a processor control circuit 7. 10 is a diagram illustrating a configuration example of a special function register in Embodiment 2. FIG. 10 is a flowchart illustrating an example of an abnormality determination process performed by a processor module 2 according to the second embodiment. 10 is a flowchart illustrating an example of an abnormality determination process performed by a processor module 2 according to a third embodiment. FIG. 10 is a diagram illustrating a configuration example of a special function register according to a fourth embodiment. (A) is a timing chart showing an operation when a cache miss occurs even in the processor module 2 set with a low priority when a cache miss occurs in the processor module 1 and a cache read operation is performed. . (B) is a timing chart showing an operation when a cache miss occurs in the processor module 1 when a cache miss occurs in the processor module 2 set with a low priority and a cache read operation is performed. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment when the present invention is applied to an IC chip.

  First, a schematic configuration of the IC chip according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a schematic configuration example of the IC chip C. The IC chip C is an example of the electronic information recording medium of the present invention. The IC chip C is used by being mounted on a cash card, a credit card, an employee card or the like. Alternatively, the IC chip C is incorporated in a communication device such as a smartphone or a mobile phone. The IC chip C may be configured by being directly incorporated on the circuit board of the communication device.

  As shown in FIG. 1, the IC chip C includes a processor module 1, a processor module 2, a RAM (Random Access Memory) 3, a ROM (Read Only Memory) 4, an NVM (Nonvolatile Memory) 5, an I / O circuit 6, and A processor control circuit 7 is provided, and these components are connected to a bus 8. The bus 8 includes an address bus and a data bus. The IC chip C shown in FIG. 1 includes two processor modules, but may include three or more processor modules. The RAM 3, the ROM 4, and the NVM 5 are an example of a storage unit that stores program codes or data. For example, the ROM 4 or the NVM 5 stores an OS, an application program (consisting of a plurality of program codes), and an operation control program of the present invention. A flash memory or “Electrically Erasable Programmable Read-Only Memory” is applied to the NVM 5. The I / O circuit 6 serves as an interface with an external device. In the case of the contact type IC chip C, the I / O circuit 6 includes, for example, eight terminals C1 to C8. For example, the C1 terminal is a power supply terminal, the C2 terminal is a reset terminal, the C3 terminal is a clock terminal, the C5 terminal is a ground terminal, and the C7 terminal is a terminal for communicating with an external device. On the other hand, in the case of the non-contact type IC chip C, the I / O circuit 6 includes, for example, an antenna and a modulation / demodulation circuit. Examples of external devices include IC card issuers, ATMs, ticket gates, and authentication gates. Alternatively, when the IC chip C is incorporated in a communication device, the external device corresponds to a control unit that functions as a communication device. Furthermore, examples of external devices include abnormality detection sensors such as voltage sensors, temperature sensors, and optical sensors. The abnormality detection sensor may be mounted on the IC chip C.

  The processor modules 1 and 2 include CPU cores 11 and 21, caches 12 and 22, respectively. The processor module 1 and the processor module 2 have the same configuration, but execute different processes according to their roles. For example, the processor module 1 performs processing (hereinafter referred to as “main processing”) according to a command input from an external device via the I / O circuit 6. On the other hand, the processor module 2 performs, for example, a redundant sub-process (for example, an abnormality detection process and an abnormality determination process) different from the main process. Although not shown, each of the CPU cores 11 and 21 includes an arithmetic unit, a program counter, a register, and the like. In the main process, the CPU core 11 fetches (acquires) the program code from the cache 12 into a register, interprets (decodes), and executes it. On the other hand, in the sub-process, the CPU core 21 fetches (acquires) the program code from the cache 22 to the register, interprets (decodes), and executes it. Each of the caches 12 and 22 includes a cache memory, a cache memory control unit, and the like (not shown). The cache memory control unit caches (temporarily holds) a part of the program code or data acquired from the RAM 3, the ROM 4, or the NVM 5 via the bus 8 under the control of the CPU cores 11 and 21. In addition, the cache memory control unit, for example, when the program code or data requested from the CPU core 11 does not exist in the cache memory (that is, when a cache miss occurs), the RAM 3, ROM 4, or Data transfer (memory transfer) from the NVM 5 to the cache memory is performed. The caches 12 and 22 may be physically separated from those used for program code and those used for data. A part of the caches 12 and 22 may be shared by a plurality of processor modules.

  The processor control circuit 7 includes the setting means, the determination means, and the control means of the present invention. Among the processor modules 12 and 22, a processor module (12 or 22) to be stopped when a predetermined situation occurs is set in advance, and the predetermined When it is determined that the above situation has occurred, the operation of the set processor module is stopped, and the operation of the processor modules other than the stopped processor module is performed. Thereby, it is possible to preferentially operate one of the plurality of processor modules depending on the situation. The processor control circuit 7 is configured by, for example, hardware, but the processing by the processor control circuit 7 may be configured by software. In this case, the processor control circuit 7 is a computer that performs the operation control of the present invention. According to the program, it functions as setting means, determination means, and control means of the present invention.

  Next, an operation example of the IC chip C according to the present invention will be described separately in the first to fourth embodiments.

Example 1
First, the operation of the first embodiment will be described with reference to FIGS. In the first embodiment, the predetermined situation is an interrupt event. In the first embodiment, the processor control circuit 7 includes a special function register. FIG. 2 is a diagram illustrating a configuration example of the special function register according to the first embodiment. In the example of FIG. 2, a module operation display register 71, a generated event setting register 72, a stop event setting register 73, and module operation setting registers 74a to 74h are shown as special function registers. In the example of FIG. 2, each register is configured with 8 bits b (bits) 1 to b8, but is not limited thereto.

  The module operation display register 71 is a register indicating the current operation state (0: stop, 1: operation) of the processor module 1 (PM1) and the processor module 2 (PM2). In the example of FIG. 2, b <b> 1 of the register 71 indicates the operation state of the processor module 1, and b <b> 2 of the register 71 indicates the operation state of the processor module 2. Also, b1 and b2 (“0” or “1”) of the module operation display register 71 can be switched by the processor control circuit 7 or the processor modules 1 and 2 (in other words, can be switched and set by software). It has become. As a result, the operating states of the processor modules 1 and 2 are switched.

  The generated event setting register 72 is a register in which the generated interrupt event is set (set in hardware). Interrupt events include, for example, data reception (data (including command) reception via the I / O circuit 6), data transmission (data transmission via the I / O circuit 6), NVM update, abnormality detection, software interrupt, etc. There are multiple types. The abnormality detection includes abnormality detection by hardware (for example, an abnormality detection sensor) and abnormality detection by software. In the example of FIG. 2, when the interrupt event that has occurred is data reception, b1 of the register 72 is changed from “0” to “1”. For example, when the generated interrupt event is data transmission, b2 of the register 72 is changed from “0” to “1”. For example, when the generated interrupt event is an abnormality detection, b7 of the register 72 is changed from “0” to “1”.

  The stop event setting register 73 is a register in which an interrupt event for stopping the processor module 1 or the processor module 2 is set (software setting). This setting is performed by the processor control circuit 7 in accordance with an instruction input via the I / O circuit 6 from a user of the IC card, for example. For example, as shown in FIG. 2, when b1 of the register 73 is set to “1”, the processor module 1 or the processor module 2 is stopped when data reception occurs. Which of the processor module 1 and the processor module 2 is to be stopped is set in the module operation setting registers 74a to 74h. For example, the module operation setting register 74a is a register corresponding to data reception. In the example of FIG. 2, b1 of this register 74a is set to “1” (processor module 1 is operating), and b2 of this register 74a. Is set to “0” (the processor module 2 is stopped). With this setting, it is possible to prevent the occurrence of a communication error due to the fact that processing cannot be performed for a certain period when data is received. Thus, the processor control circuit 7 can set a processor module to be stopped when the interrupt event occurs for each of a plurality of different interrupt events.

  FIG. 3 is a flowchart illustrating an example of processing performed by the processor control circuit 7. The process shown in FIG. 3 is repeatedly executed at a predetermined cycle. In the process shown in FIG. 3, first, the processor control circuit 7 determines whether or not an interrupt event has occurred (step S1). When “1” is set in any bit in the occurrence event setting register 72, it is determined that an interrupt event has occurred. For example, when “1” is set to b1 in the occurrence event setting register 72, it is determined that an interrupt event “data reception” has occurred. If it is determined that an interrupt event has occurred (step S1: YES), the process proceeds to step S2. On the other hand, when it is determined that no interrupt event has occurred (step S1: NO), the process ends.

  In step S2, the processor control circuit 7 determines whether or not the generated interrupt event is an interrupt event that stops the processor module. When “1” is set in the bit corresponding to the generated interrupt event in the stop event setting register 73, it is determined that the generated interrupt event is an interrupt event that stops the processor module. For example, when “1” is set to b1 in the stop event setting register 73, it is determined that the interrupt event “data reception” that has occurred is an interrupt event that stops the processor module. When it is determined that the generated interrupt event is an interrupt event for stopping the processor module (step S2: YES), the process proceeds to step S3. On the other hand, when it is determined that the event is not an interrupt event that stops the processor module (step S2: NO), the processing ends.

  In step S3, the processor control circuit 7 specifies a processor module to be stopped. For example, when the interrupt event to be stopped is “data reception”, the processor module corresponding to the bit set to “1” in the module operation setting register 74a corresponding to data reception is specified as the processor module to be stopped (see FIG. In the example of 2, the processor module 2 specifies).

  Next, the processor control circuit 7 determines whether or not the processor module specified in step S3 is operating (step S4). When “1” is set in the bit corresponding to the specified processor module in the module operation display register 71, it is determined that the processor module is operating. If it is determined that the identified processor module is operating (step S4: YES), the process proceeds to step S5. On the other hand, when it is determined that the identified processor module is not in operation (step S4: NO), the processing ends.

  In step S5, the processor control circuit 7 stops the operation of the processor module specified in step S3. For example, in the module operation display register 71, the processor module stops operation (for example, sub-processing) by switching the bit corresponding to the specified processor module (for example, processor module 2) from “1” to “0”. Let

  Thereafter, the processor control circuit 7 performs a return process of the processor module. In this return process, when the processor control circuit 7 detects the end of the process corresponding to the interrupt event that has occurred (for example, the process corresponding to the data reception by the processor module 1 (for example, the main process)), in step S5 described above. The operation of the stopped processor module is restored. For example, in the module operation display register 71, the operation of the processor module is restored by switching the bit corresponding to the stopped processor module (for example, processor module 2) from “0” to “1”. When the process corresponding to the generated interrupt event is completed, “0” is set in the bit corresponding to the interrupt event in the generated event setting register 72.

  As described above, according to the first embodiment, one of the plurality of processor modules 1 and 2 can be preferentially operated in response to the occurrence of an interrupt event (for example, data reception). Therefore, for example, in a process that requires high speed such as communication with an external device, a response can be returned quickly.

(Example 2)
Next, the operation of the second embodiment will be described with reference to FIGS. In the second embodiment, the predetermined situation is hardware abnormality detection. Also in the second embodiment, the processor control circuit 7 includes the same special function register as that of the first embodiment. FIG. 4 is a diagram illustrating a configuration example of the special function register according to the second embodiment. As shown in FIG. 4, the second embodiment is different from the first embodiment in the setting contents of the stop event setting register and the module operation setting register, but the other configurations are the same as those of the first embodiment. In the example of FIG. 4, b7 of the stop event setting register 73 is set to “1”, and b1 of the module operation setting register 74g corresponding to the abnormality detection is set to “0” (the processor module 1 is stopped). B2 of the register 74g is set to "1" (the processor module 2 operates). In such a setting, when “abnormality detection” (abnormality detection by hardware) occurs as an interrupt event, it is determined in step S2 shown in FIG. 3 that the generated interrupt event is an interrupt event that stops the processor module. The Then, in step S3 shown in FIG. 3, the processor module 1 is specified as the processor module to be stopped, the operation of the processor module 1 is stopped (that is, abnormally stopped), and the operation of the processor module 2 is performed. In this operation, the processor module 2 executes an abnormality determination process.

  FIG. 5 is a flowchart illustrating an example of an abnormality determination process performed by the processor module 2 according to the second embodiment. When the processing shown in FIG. 5 is started, the processor module 2 confirms the cause of the detected abnormality (step S11), and whether the detected abnormality is a problem abnormality (preset). Is determined (step S12). Here, the abnormality that is a problem is an abnormality that cannot occur during normal operation, and is an abnormality that requires the IC chip C to be stopped. For example, examples of abnormalities that cause problems include high voltage detection abnormalities, high temperature detection abnormalities, low temperature detection abnormalities, and light detection abnormalities. The high voltage detection abnormality refers to an abnormality in which a high voltage equal to or higher than a threshold value (predetermined voltage) is detected by the voltage sensor. The high temperature detection abnormality is an abnormality in which a high temperature equal to or higher than a threshold (predetermined temperature) is detected by the temperature sensor. The low temperature detection abnormality is an abnormality in which a low temperature below a threshold is detected by a temperature sensor. The light detection abnormality refers to an abnormality (for example, due to a laser attack) in which light of a threshold value (predetermined lux) or more is detected by the optical sensor. On the other hand, an abnormality that does not cause a problem is an abnormality that may occur during normal operation, such as an electrical noise or a problem of a contact portion. For example, abnormalities that do not cause problems include glitch abnormalities for power supplies, low voltage detection abnormalities, high frequency detection abnormalities, and the like.

  When the processor module 2 determines that the detected abnormality is a problem abnormality (step S12: YES), the processor module 2 stops all processing (step S13). On the other hand, if the processor module 2 determines that the detected abnormality is not a problem abnormality (step S12: NO), the processor module 2 checks the abnormality detection counter (step S14). Here, the abnormality detection counter is a counter that counts the number of abnormal detections that do not cause a problem. For example, the abnormality detection counter is provided in the NVM 5. Next, the processor module 2 determines whether or not the value of the abnormality detection counter is a preset upper limit value (step S15). If the value of the abnormality detection counter is the upper limit value (step S15: YES), the processor module 2 stops all processing (step S13). On the other hand, when the value of the abnormality detection counter is not the upper limit value (step S15: NO), the processor module 2 updates the abnormality detection counter (that is, increments the value of the abnormality detection counter by 1) (step S16). Next, the processor module 2 (that is, the processor module 2 other than the stopped processor module 1) restores the operation of the stopped processor module 1 (step S17). For example, the processor module 2 gives a command to the processor control circuit 7 and switches the bit corresponding to the processor module 1 from “0” to “1” in the module operation display register 71 to restore the operation of the processor module 1.

  As described above, according to the second embodiment, one of the plurality of processor modules 1 and 2 can be preferentially operated in response to the occurrence of an abnormality detection interrupt event. Therefore, it is possible to prevent an unauthorized situation from spreading by proceeding with the main process when an abnormality is detected.

(Example 3)
Next, the operation of the third embodiment will be described with reference to FIG. In the third embodiment, the predetermined situation is abnormality detection by software. In the third embodiment, the processor control circuit 7 may include the same special function registers as those in the second embodiment. However, the generation event setting register 72, the stop event setting register 73, and the module operation setting registers 74a to 74h Not used. FIG. 6 is a flowchart illustrating an example of the abnormality determination process performed by the processor module 2 according to the third embodiment. The abnormality detection process shown in FIG. 6 is started when, for example, the processor module 2 detects an abnormality according to the abnormality detection program (that is, abnormality detection by software occurs). As an abnormality detection method by software, CRC (Cyclic Redundancy Check) check, RAM value check, NVM value check, program processing value check, and the like can be cited. In the CRC check, an abnormality is detected when a value held in advance is different from a value calculated by CRC calculation. In the RAM value check, when the value stored in the RAM 3 is different from the expected value, an abnormality is detected. In the NVM value check, an abnormality is detected when the value stored in the NVM 5 is different from the expected value. In the program processing value check, an abnormality is detected when a value obtained from the program processing flow is different from an expected value.

  When the process shown in FIG. 6 is started, the processor module 2 stops the operation of the processor module 1 (step S21). For example, the processor module 2 gives a command to the processor control circuit 7 and stops the operation of the processor module 1 by switching the bit corresponding to the processor module 1 from “1” to “0” in the module operation display register 71. Next, the processor module 2 confirms the cause of the abnormality detected (step S22), and determines whether or not the abnormality detected is a problem abnormality (preset) (step S23). Here, examples of abnormalities that cause problems (that is, abnormalities that cannot occur during normal operation) include abnormalities caused by a RAM value check, abnormalities caused by a program processing value check, and the like. On the other hand, as an abnormality that does not cause a problem (that is, an abnormality that may occur during normal operation), for example, an abnormality caused by an NVM value check may be cited.

  If the processor module 2 determines that the detected abnormality is a problem abnormality (step S23: YES), the processor module 2 stops all processing (step S24). On the other hand, if the processor module 2 determines that the detected abnormality is not a problem abnormality (step S23: NO), the processor module 2 checks the abnormality detection counter (step S25). The processing after step S26 is the same as the processing after step S15.

  As described above, according to the third embodiment, any one of the plurality of processor modules 1 and 2 can be preferentially operated in accordance with abnormality detection by software. Therefore, it is possible to prevent an unauthorized situation from spreading by proceeding with the main process when an abnormality is detected.

Example 4
Next, the operation of the fourth embodiment will be described with reference to FIGS. In the fourth embodiment, the predetermined situation is a program code or data cache miss. Also in the fourth embodiment, the processor control circuit 7 includes a special function register. FIG. 7 is a diagram illustrating a configuration example of the special function register according to the fourth embodiment. In the example of FIG. 7, a priority event setting register 75 and module priority order setting registers 76 and 77 are shown as special function registers. In the fourth embodiment, the processor control circuit 7 may include the same special function registers as those in the first embodiment, but the occurrence event setting register 72, the stop event setting register 73, and the module operation setting registers 74a to 74h Not used.

  The priority event setting register 75 is a register in which an interrupt event to be preferentially processed by the processor module 1 or the processor module 2 is set (software setting). This setting is performed by the processor control circuit 7 in accordance with an instruction input via the I / O circuit 6 from a user of the IC card, for example. For example, as shown in FIG. 7, when b1 of the register 75 is set to “1”, the interrupt event to be preferentially processed is data reception.

  The module priority setting register 76 is a register for setting the priority of the processor module 1 when an interrupt event set by the priority event setting register 75 occurs. The module priority setting register 77 is a priority event setting register 75. This is a register in which the priority order of the processor module 2 is set when the interrupt event set in (1) occurs. For example, a smaller value in such a register has a higher priority. A processor module with a low priority is a processor module that is stopped when a cache miss occurs. In the example of FIG. 7, since the value “00” set in the module priority setting register 76 is smaller than the value “01” set in the module priority setting register 77, the processor module 2 has a cache miss. Stopped when it occurs. Instead of setting the priority order, a processor module to be stopped when a cache miss occurs may be set.

  When the processor control circuit 7 according to the fourth embodiment determines that a cache miss has occurred, the processor whose priority order is set low in the module priority order setting register 76 (that is, set to be stopped when a cache miss occurs). The operation of the module is stopped and the operation of the processor module other than the processor module to be stopped is performed, and a cache read operation (that is, data transfer) for acquiring the program code or data from the RAM 3 or the like via the bus 8 is performed. . This makes it possible to stop the operation of the processor module with the lower priority set at the time of bus contention and give priority to the operation of the other processor module.

  FIG. 8A shows that when a cache miss occurs in the processor module 1 and a cache read operation is performed, even in the processor module 2 set with a low priority, a cache miss (a cache miss during data reception processing execution) is performed. It is a timing chart which shows the operation | movement when) occurs. In the example of FIG. 8A, when the CPU core 11 of the processor module 1 and the CPU core 21 of the processor module 2 are operating together, first, when a cache miss occurs in the processor module 1, the CPU core 11 stops the operation, and the cache 12 (cache memory control unit) starts a cache read (that is, data transfer) operation. That is, during the cache read operation by the cache 12, the CPU core 11 is not operating, but the cache 12 is operating, so the processor module 1 is operating. If a cache miss occurs in the processor module 2 during the cache read operation by the cache 12, the CPU core 21 stops operating and the cache 22 (cache memory control unit) waits for the cache read operation. That is, during the cache read operation by the cache 12, both the CPU core 21 and the cache 22 stop operating, so that the processor module 2 is stopped (that is, the operation of the processor module 2 is stopped). Then, when the cache read operation by the cache 12 is completed, the CPU core 11 resumes the operation. At this time, the cache 22 starts a cache read operation (that is, restores the operation of the processor module 2). Then, when the cache read operation by the cache 22 is completed, the CPU core 21 resumes the operation.

  On the other hand, FIG. 8B shows that when a cache miss occurs in the processor module 2 set with a low priority and a cache read operation is performed, the processor module 1 also performs a cache miss (during execution of data reception processing). 6 is a timing chart showing an operation when a (cache miss) occurs. In the example of FIG. 8B, when the CPU core 11 of the processor module 1 and the CPU core 21 of the processor module 2 are operating together, first, when a cache miss occurs in the processor module 2, the CPU core 21 stops the operation, and the cache 22 (cache memory control unit) starts a cache read operation. If a cache miss occurs in the processor module 1 during the cache read operation by the cache 22, the cache 22 temporarily stops the cache read operation (that is, stops the operation of the processor module 2), and the cache 12 Start reading operation. Then, when the cache read operation by the cache 12 is completed, the CPU core 11 resumes the operation. At this time, the cache 22 resumes the cache read operation (that is, restores the operation of the processor module 2). Then, when the cache read operation by the cache 22 is completed, the CPU core 21 resumes the operation.

  As described above, according to the fourth embodiment, one of the plurality of processor modules 1 and 2 can be preferentially operated according to the occurrence of a cache miss. Therefore, for example, in a process that requires high speed such as communication with an external device, a response can be returned quickly.

  In the above embodiment, the IC chip C has been described as an example of the electronic information recording medium. However, the present invention may be applied to, for example, an embedded microcomputer other than the IC chip C.

1, 2 Processor module 3 RAM
4 ROM
5 NVM
6 I / O circuit 7 Processor control circuit 8 Buses 11 and 21 CPU cores 12 and 22 Cache C IC chip

Claims (3)

A storage unit that stores program code or data, and a plurality of processor modules that cache a part of the program code or data acquired from the storage unit via a bus, and that perform different processes according to roles An electronic information recording medium comprising a processor module,
Setting means for presetting the processor module to be stopped when a cache miss of the program code or data occurs among the plurality of processor modules;
Determining means for determining whether or not the cache miss has occurred;
When the determination unit determines that the cache miss has occurred in a plurality of processor modules including the processor module preset by the setting unit, the operation of the processor module preset by the setting unit is stopped. An operation of the processor module other than the processor module to be stopped, the program code subject to the cache miss in the processor module other than the processor module to be stopped from the storage unit, or Control means for performing an operation of acquiring data ;
An electronic information recording medium comprising: A storage unit that stores program code or data, and a plurality of processor modules that cache a part of the program code or data acquired from the storage unit via a bus, and that perform different processes according to roles An operation control method for the processor module in an electronic information recording medium comprising a processor module,
A setting step for presetting the processor module to be stopped when a cache miss of the program code or data occurs among the plurality of processor modules;
A determination step of determining whether or not the cache miss has occurred;
When the determination step determines that the cache miss has occurred in a plurality of processor modules including the processor module preset in the setting step, the operation of the processor module preset in the setting step is stopped. The operation of the processor module other than the processor module to be stopped, and the program code or data subject to the cache miss in the processor module other than the processor module to be stopped from the storage unit A step of performing an operation of acquiring
An operation control method for a processor module, comprising: A storage unit that stores program code or data, and a plurality of processor modules that cache a part of the program code or data acquired from the storage unit via a bus, and that perform different processes according to roles A computer in an electronic information recording medium comprising a processor module;
A setting step for presetting the processor module to be stopped when a cache miss of the program code or data occurs among the plurality of processor modules;
A determination step of determining whether or not the cache miss has occurred;
When the determination step determines that the cache miss has occurred in a plurality of processor modules including the processor module preset in the setting step, the operation of the processor module preset in the setting step is stopped. The operation of the processor module other than the processor module to be stopped, and the program code or data subject to the cache miss in the processor module other than the processor module to be stopped from the storage unit A step of performing an operation of acquiring
An operation control program for a processor module, characterized in that

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