JPH0546477A - Cathe memory control method - Google Patents

Abstract

PURPOSE:To prevent the content of the cathe memory from being updated every time and to improve the performance when data in a space with the far distant address is required only once or the alternate access to the distant address is required among the processings executing at present. CONSTITUTION:The cathe memory control method is provided with a first register 17 and a second register 18 having the same bit width with an address indexing an address array 14, a comparator circuit 20 comparing an address value indexing an address array with the first and second registers, a means storing a value to the first and second registers, and first flag 25 and a second flag 26 indicating the values of the 1st and 2nd registers are effective. When the 1st and the 2nd flags are effective, the content of the cathe memory is not updated even at the time of mishitting when the address value is equal to the 1st or the 2nd register value or when it takes a value between the 1st and the 2nd registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method.

[0002]

2. Description of the Related Art When a conventional cache memory has a mishit, a processing device having a cache memory reads out data of a certain size including necessary data from an external storage device and uses it for processing. At the same time, the contents of the corresponding area of the cache memory are updated.

[0003]

In the above-described conventional control method, when the data in the space with a large distance from the address is needed only once in the process currently being executed, or the space with a large distance from the address is required. When the access becomes necessary alternately, the contents of the cache memory are updated every time and the performance deteriorates.

[0004]

According to a method of controlling a cache memory of the present invention, in a cache memory, a first register and a second register having the same bit width as an address for indexing an address array, and the address array are indexed. Comparing circuit for comparing the address value with the first and second registers, means for storing an arbitrary value in the first and second registers, and the values of the first and second registers being valid respectively Has a first flag and a second flag indicating
When the first and second flags are valid, the value of the address value is equal to the value of the first register or the value of the second register, or the value of the first register and the second register. When taking a value between the values of the registers of, the contents of the cache memory are not updated even if a mishit occurs.

[0005]

Embodiments of the present invention will now be described with reference to the drawings. In the description of this embodiment, a certain signal value is "1".
It has a meaning when it takes a value of, and is said to be effective.

FIG. 1 is a block diagram showing an embodiment of a cache memory control method of the present invention.

Referring to FIG. 1, inside the processor 10 are the following: The processing execution unit 11 is provided in the processing device 10.
There is. The process execution unit 11 has a command register 12 and an address register 13 for memory access. The address register 13 has 24 bits, and the upper 1
It is divided into 0 bit and lower 14 bits, and the upper part,
The term lower part is used. Further, the upper 10 bits of the 14 bits of the lower part will be referred to as the lower part 1. There is an address array 14 and a data array 15 that stores data corresponding to the address array 14. The cache memory referred to in this example is an address array 14 and a data array 15.
Is a combination of. The lower part 1 of the address register 13 searches the address array 14. Lower part 1 of 1
Corresponding to 0 bits, the address array 14 has a size of 1024 words. The address array 14 stores the upper 10 bits of the address of the data stored in the data array 15 at the position indicated by the value of the lower portion 1. Address array 14 addressed by the value of lower part 1
Is output from the upper part of the address register 13 and the matching circuit 16
Compared by The data array 15 has a size of 1024 blocks. One block in this example has a size of 16 bytes. The data width to be stored is 16 bytes corresponding to 4 bits of the address obtained by subtracting the lower part 1 from the lower part of the address register 13. Address register 1
The lower part 1 of 3 addresses the data array 15 as well as the address array 14. When the match circuit 16 detects a match between the output of the address array 14 and the upper part of the address register 13, the output of the data array 15 at this time becomes the data of the address indicated by the address register 13.

Control bits 23 and 24 exist in the command register 12 and control registers 17 and 18, which will be described later. The register 17 is a first register that stores the lower part 1 of the address, and the register 18 is a second register that stores the lower part 1 of the address. When the control bits 23 and 24 of the command register 12 are “10” in the register 17, the control bits 23 and 24 are “0” in the register 18.
When it is "1", the lower part 1 of the output of the address register 13 is stored in each. The control bits 23 and 24 are "0".
When it is "0", nothing is done, and when it is "11", the flags 25 and 26 in the write instruction circuit 19 described later are reset. The write instruction circuit 19 moves to the registers 17 and 18 according to the value of the command register 12. A flag 25 indicating that the register 17 is valid and a flag 2 indicating that the register 18 is valid.
Have 6 The comparison circuit 20 includes the lower part 1 of the outputs of the registers 17 and 18 and the output of the address register 13 and the matching circuit 16
Is a circuit for generating the cache update inhibition signal 30 from the output of When the output of the coincidence circuit 16 is not valid, the cache memory update inhibition signal 30 of the output of the comparison circuit 20 is compared by the combination of the flags 25 and 26 as follows.
To enable. {(Flag 25, flag 26) = (0,
0)}, the comparison operation is not performed and the cache update suppression signal 30 is not valid. When {(flag 25, flag 26) = (1,0)}, the output of the register 17 and the lower part 1 of the address register 13 are compared and are equal or the lower part 1 of the address 13 is lower than the value of the register 17. When it is larger, the cache update inhibition signal 30 is valid. When {(flag 25, flag 26) = (0, 1)}, the output of the register 18 is equal to the lower part 1 of the address register 13 or the lower part 1 of the address 13 is smaller than the value of the register 18. Cache update suppression signal 3
Enable 0. {(Flag 25, flag 26) =
When (1, 1)}, the lower part 1 of the address register 13
Is equal to the value of register 17, equal to the value of register 18 or greater than the value of register 17 and register 1
When it is smaller than the value of 8, the cache update inhibition signal 30 is valid.

The control circuit 21 is a circuit for accessing the storage device 40. The bus 31 is a bus that connects the processing device 10 and the storage device 40.

Areas that are frequently used by the processing to be executed are known at the time of designing the system. Process execution unit 1
1 has an area that is frequently used, and if you want to leave it in the cache, once access all the area, first set the minimum address of that area to 10 in the control bits 23 and 24 of the command register 12. to access. As a result, the flag 25 is enabled and the register 1
The write instruction signal 27 for 7 is enabled, and the lower part 1 of the address register 13 is stored in the register 17. Then set the maximum address to control bits 23 and 24 to "0".
The memory access is executed by setting it to "1". As a result, the flag 26 is enabled, the write instruction signal 28 for the register 18 is enabled, and the lower part 1 of the address register 13 is stored in the register 18. After that, the specified range is the matching circuit 1 at the time of the write memory access.
Update is allowed only when the outputs of 6 match.

In this example, the size of the data read from the storage device 40 in the case of a mishit is 16 bytes,
This is called one block. It is assumed that the block exists at every 16-byte boundary in the storage device 40, and one block containing necessary data is loaded into the data array 15. At this time, the upper part of the address register 13 is stored in the area of the address array 14 designated by the lower part 1 of the address register 13.

It is now assumed that the flag 25, the flag 26, the address register 13, the register 17, the register 18, the address array 14 and the data array 15 are in the states shown in FIG. At this time, since the flags 25 and 26 are invalid, the comparison circuit 20 does not operate at all. This is the case where this patent is not functioning. If a mishit occurs in this state, the contents of the cache memory (address array 14
And the data array 15) is updated.

It is assumed that the state of FIG. 2 is the initial state and the address register 13 sequentially takes the values as shown in FIG. 3 from the next step, and the memory access occurs one after another. Address array 14 corresponding to the first memory access (1)
Area contains the value of a, and address register 1
Address array 1 because it cannot match the upper part of 3
4. The data array 15 is updated. Thereafter, the upper part of (2) is compared with b and the upper part of (3) is compared with c, but since they do not match, the address array 14 and the data array 15 are updated every time. Block load occurs 10 times in total.

Next, it is assumed that the flag 25, the flag 26, the address register 13, the register 17, the register 18, the address array 14 and the data array 15 are in the states shown in FIG. The difference from FIG. 2 is that the flags 25 and 26 are valid and the values are stored in the registers 17 and 18, respectively. At this time, it is assumed that memory accesses are sequentially generated as shown in FIG. Since the lower part 1 of the address is the address sandwiched between the register 17 and the register 18, when the upper part of the address register 13 does not match the output of the address array 14, a mishit occurs and the storage device 40 is accessed, but the cache is accessed. The contents of memory are not updated. If it changes as shown in Fig. 3, (1) (3) (5)
(7) In (9), the lower part 1 of the address is the register 17, 1
Although it is sandwiched between 8's, the output of the address array 14 does not match, so a miss hit occurs and the storage device 40 is accessed, but a cache hit occurs at (2) (4) (6) (8) (10). The storage device 40 is not accessed. Therefore, when the initial state is shown in FIG.
When the initial state is shown in FIG. 4 even though the number of accesses to is 10 times, the performance is improved by the amount reduced to 1/2, which is 5 times.

[0015]

As described above, according to the cache memory control method of the present invention, when the data in the space far apart from the address is needed only once in the process currently being executed, or when the address is large. This prevents the contents of the cache memory from being updated every time when it is necessary to alternately access a distant space, which leads to an improvement in performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cache memory control method of the present invention.

FIG. 2 is an address register 13, a register 17, a register 18, and a flag 2 showing an example of the operation in this embodiment.
5, flag 26, address array 14, data array 1
It is a figure which shows the state of 5.

FIG. 3 is a storage device 4 showing an example of an operation in this embodiment.
0 state, address register 13, address array 1
4 is a diagram showing changes in the data array 15. FIG.

FIG. 4 is an address register 13, a register 17, a register 18, and a flag 2 showing an example of the operation in this embodiment.
5, flag 26, address array 14, data array 1
It is a figure which shows the state of 5.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 processor 11 process execution part 12 command register 12 13 address register 13 14 address array 15 data array 16 coincidence circuit 17, 18 register 19 write instruction circuit 20 comparison circuit 21 control circuit 23, 24 control bit 25, 26 flag 27 register 17 Write instruction signal for register 28 write instruction signal for register 30 cache memory update inhibition signal 30 31 bus 40 storage device

Claims (3)

[Claims] 1. In a cache memory, a first register and a second register having the same bit width as an address for indexing an address array are compared with an address value for indexing the address array and the first and second registers. A comparator circuit for storing an arbitrary value in the first and second registers, and a first flag and a second flag indicating that the values in the first and second registers are valid, respectively. Then
When the first and second flags are valid, the value of the address value is equal to the value of the first register or the value of the second register, or the value of the first register and the second register. A method for controlling a cache memory, wherein the value of the cache memory is not updated even if a mishit occurs when the value is between the values of the registers. 2. The cache memory according to claim 1, wherein when the first flag is valid and the second flag is invalid, the value of the address value for searching the address array is the first register. And a value larger than the value of the first register, the contents of the cache memory are not updated even if a mishit occurs. 3. The cache memory according to claim 1, wherein when the first flag is invalid and the second flag is valid, the value of the address value for searching the address array is the second register. And a value smaller than the value of the second register, the cache memory control method is characterized in that the contents of the cache memory are not updated even if a mishit occurs.