JPH02253358A - Cache memory - Google Patents

Abstract

PURPOSE:To set the cache hit rate in accordance with the priority of a process by increasing the value of a reference area for the data to which a process having high priority had an access. CONSTITUTION:When one of processors 1-4 produces an access request to a certain address, the value is produced in accordance with the priority of the processor that is carried out by the processor. When a cache has a hit, an access is given to the necessary data and at the same time the value added with the value corresponding to the priority is written into a reference area 53 in a block where the data is stored. Then the value of the reference area of each block is periodically decreased. When the value of the reference area is equal to 0, the corresponding block is defined as a candidate for replacement. However it is hard to define the data to which a process of high priority had an access as a candidate for replacement since the value of the reference area is large. As a result, the hit rate is increased for a cache memory of a process having high priority.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a cache memory.0 Prior Art In a conventional cache memory, a method for replacing blocks is FIFO (First-in-First-Input).
Out) method and LRU (Least Recently
There are several methods such as ``Used'', but the method that is actually most used from the viewpoint of cost and efficiency is a method that approximates LRU. FIG. 2 shows an example of the method of approximating I and RU, where 1 is the address generated by the processor, 2 is the address tag part in the address, 3 is the buffer, and 4 is the block in the buffer. , 6 indicates an address tag within the block, 6 indicates data within the block, 7 indicates a reference bit within the block, and 8 indicates a replacement pointer.

In the conventional cache memory configured as described above, reference bit 7 of a block accessed in response to a request from a processor is set to 1. On the other hand, the reference bit 7 of the block 4 indicated by the replacement pointer 8 is set to 0, and the replacement pointer 8 is advanced to the next block. If the reference bit of a certain block is 0 at a certain point in time, this indicates that this block has never been referenced since the reference bit was set to 0, and is made a candidate for replacement.

Problem to be Solved by the Invention However, in the above replacement method, when a plurality of processors that refer to one cache are each executing a process, and each of the processes has a priority, the cache hit rate of the executed process is depends on the locality of the program of each process and what other processes are being executed at the same time as the process is being executed, and does not depend on the priority of the process.

In view of this, the present invention provides a cache memory that allows a plurality of processors that refer to one cache as described above to make the cache hit rate of each executing process dependent on the priority of the process. The purpose is to provide

Means for Solving the Problems The present invention provides a cache memory that includes a buffer made up of a plurality of blocks and a control circuit that controls data replacement in each block, and that can be accessed by a plurality of processors. means having a reference area provided with a plurality of reference bits in the block, and writing a value corresponding to the priority of a process being executed by the processor into the reference area of a block accessed in response to a request from the processor; A cache memory characterized in that it has a control circuit equipped with means for subtracting a value of a reference area.

According to the above-described configuration, when one processor among a plurality of processors connected to a cache memory issues an access request to a certain address, the priority of the process being executed by the processor is determined at the same time. Generates a value according to the priority, and if the cache is hit, a value corresponding to the priority is written to the reference area in the block where the data is stored at the same time as the necessary data is accessed. If not, read the necessary data block from the main memory into the buffer 1 memory in the cache memory, and at the same time as accessing the necessary data, write a value according to the priority to the reference area in the block where the data is stored. . The value of the reference area of each block is periodically decremented, and if the value of the reference area is 0, the block is considered a replacement candidate, but the data accessed by a high priority process is Since the value is high, it becomes a candidate for replacement. Conversely, since data accessed by a low priority process is easily replaced, the hit rate of the high priority process to the cache memory increases.

Embodiment FIG. 1 shows a schematic configuration diagram of a cache memory in an embodiment of the present invention in which it is combined with a plurality of 10 setters. 1, 2, 3.4 are processors, 11 is an address generated by processor 1, and 12 is an address generated by processor 1.
is an address tag in the address, 13 is a word selection part in the address, 14 is the priority of the process being executed by the processor, 6 is a buffer, 61 is an address tag in the buffer, 52 is a word selection part in the buffer 63 is a reference area in the buffer, 6 is a hit signal, 7 is a data line, and 8 is an interface section with the processor.

The operation of the cache memory of this embodiment configured as described above will be described below. When one processor 1 among a plurality of processors connected to a cache memory through an interface section 8 issues an access request to a certain address 11, a request is made for access to a certain address 11 according to the priority of the process currently being executed by the processor. Generates a value of 14.

The address tag in the address is compared with the address tag in the cache memory, and if there is a hit in the cache, a hit signal is output, and the necessary data from the data block of the hit block is output from the data line 7 to the word selection unit 13. The value of the reference area 6 corresponding to the block containing the output data is read, the value and the value corresponding to the priority level 14 generated from the processor 1 are added, and the value is added to the reference area 6. is written. If the cache is not hit, a control circuit (not shown in the diagram) that controls data replacement searches for a block whose reference area is 0, replaces the data in the block with the necessary data, and Priority 14
A value corresponding to the priority 14 generated from the processor is written into the reference area 6 of the block. The value of the reference area of each block is periodically decreased by the control circuit, and when the value of the reference area is O, that block is made a candidate for replacement.

As described in detail, according to the present invention, data accessed by a process with a high priority becomes a replacement candidate because the value of the reference area is high, and conversely, data accessed by a process with a low priority Since it is easy to replace, the cache memory hit rate of a high priority process increases, making it possible to make the cache hit rate of each executing process dependent on the priority of the process.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram when a cache memory is combined with a plurality of processors in an embodiment of the present invention;
FIG. 2 is a diagram illustrating an example of a conventional method for replacing blocks in a buffer of a cache memory. 1.2, 3.4... Processor, 11...
...Address frequently generated by processor 1, 12...
・・・Address tag in address, 13・・・・・・
Address word selection section, 14...Priority of the process being executed by the processor, 6...
Buffer 7.51...Address tag in the buffer, 62...Data block in the buffer, 53
... Reference area in the buffer, 6 ... Hit signal, 7 ... Data line, 8 ... Interface section with processor. Name of agent: Patent attorney Shigetaka Awano and 1 other figure

Claims (1)

[Claims] The reference buffer includes a buffer consisting of a plurality of blocks and a control circuit that controls data replacement of each block, and is accessible by a plurality of processors, and has a plurality of reference bits for each block of the buffer. The block having a memory area and accessed by a request from a processor includes means for writing a value corresponding to the priority of a process being executed in the processor into the reference area, and means for subtracting the value of the reference area. A cache memory characterized by having a control circuit.