JPH05120139A - Cache memory device - Google Patents

Abstract

PURPOSE:To provide a method in order to preferentially select an invalid entry in a permuting operation and also to permute the invalid entry at a high speed. CONSTITUTION:An LRU write control circuit is especially provided to write the information which defines an invalidated entry as the entry that is most previously referred to into an LRU memory 104 with use of an invalid signal 11. Thus the invalid entry is always selected with a permuting request since the preceding information is already written in the memory 104. Then the permuting operation is carried out at a high speed without using a control circuit which preferentially selects an entry where the invalid data is stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly to a control system for replacing data stored in a cache memory device of an information processing device at high speed.

[0002]

2. Description of the Related Art In the field of computer systems such as large-scale computers and microprocessors, a cache memory is composed of a small-capacity and high-speed memory, and temporarily holds a part of data in a large-capacity and low-speed main memory. By doing so, the operating speed of the computer system is improved. The large main memory is not fast enough for the central processor,
Therefore, a method has been adopted in which a small-capacity but high-speed cache memory is placed in the vicinity of the central processing unit and a part of the data is stored in the cache memory, so that the central processing unit operates without slowing down. ..

The cache memory is composed of a plurality of ways having a plurality of entries. For example, when a read access from the processor to the cache is missed, the read data from the main storage device is an empty entry in the cache. Stored in. However, if the cache is full and there is no free entry, the data of one of the plurality of entries is returned to the main storage device to make this entry a free entry, and then the above-mentioned main entry is added to this free entry. It is necessary to replace the entry that stores the read data from the storage device. The entry replacement method of selecting the entry that stores the data most recently referred to as the entry that stores the read data from the main memory, that is, the LRU (Least Recently Used) method is usually performed, and the cache memory usage efficiency is increased. We are trying to improve.

On the other hand, as described in Japanese Unexamined Patent Publication No. 1-125641, a cache which stores an invalid data which is not compatible with the data in the main memory while the entry to be replaced is selected by the LRU method. It is known to have a control circuit that preferentially replaces the entry of.

[0005]

By the way, all entries are invalid at the time when the cache memory starts to operate. On the other hand, in a private cache multiprocessor computer system having a plurality of processors and a cache memory for each processor, an invalid entry occurs in order to maintain the consistency of shared data even during normal operation. Therefore, by replacing an invalid entry with priority, it is possible to reduce the possibility that a frequently used entry will be replaced and improve the performance.

On the other hand, since the conventional cache memory has the control circuit for preferentially replacing an invalid entry as described above, sufficient consideration is not given to selecting an entry to be replaced at high speed. However, there is a problem that the copy back operation for writing back to the main memory is delayed when the rewritten entry is replaced.

An object of the present invention is to provide a method for selecting an entry to be replaced at high speed, and to provide a cache memory device which gives priority to an invalid entry when selecting a replacement entry and does not require complicated control. And

[0008]

The above-mentioned object is to provide a valid storage means for outputting a valid signal indicating validity or invalidity of data stored in an entry, an LRU storage means for outputting an LRU signal, and an invalid entry from the outside. This is achieved by providing a control means for writing the corresponding information into the LRU storage means so that when the activation signal is input, this entry is regarded as the most recently referenced entry.

[0009]

Since the entry storing the invalid data is written in the corresponding LRU storage means with the information indicating that it has been referred to most recently, it is preferentially replaced when the replacement request is made. Works like. This does not cause any inconvenience even if there are a plurality of invalid entries, and replaces the entry that has become invalid most recently.

Since the cache memory control method according to the present invention does not have a control circuit for preferentially selecting an invalid entry, it is possible to output a replacement way selection signal at high speed and copy back to the main storage device. The operation can be performed at high speed. On the other hand, the write operation to the LRU storage means by the entry invalidation signal from the outside is performed in parallel with the operation of writing the invalid signal indicating that the entry is invalid into the valid storage means, so that the speed is not lowered.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a 4-way set associative cache memory device according to an embodiment of the present invention. In FIG. 1, 101 is a row decoder for selecting a corresponding entry according to a search address, 102 is a tag memory which stores a part of the address corresponding to the data, and 103 stores whether the data is valid or invalid. Valid memory, 104 is an LRU memory that holds the replacement information of the entry, 105 is a data memory that stores data, and 106 is a match between the address stored in the tag memory 107 and a search address input from the outside. Comparing circuit 107, 107 is the comparing circuit 106
, A selection circuit for outputting the entry of the way in which the match is detected, 108 is a column decoder for selecting desired data from the entries, 110 is a control circuit for writing the reference history in the LRU memory 104, and 11 is an entry from the outside. Is an invalid signal, 12 is a cache hit signal indicating that the search address input from the outside is stored in the tag memory.

In the cache memory device according to this embodiment, the invalid signal 11 inputted from the outside is inputted to the LRU write control circuit 110, and when the entry is invalidated, the information that makes the entry the entry referred to most recently is LRU. The feature is that the data is written in the memory for use 104. FIG. 2 is an operation explanatory diagram of the 4-way LRU write control circuit 110, and the operation will be described with reference to this. As shown in FIG. 1, the tag memory 102, the valid bit memory 103, and the data memory 105 each have four sides, thereby realizing a 4-way set associative cache memory device.

In the LRU memory 104, for example, FIG.
As shown in (a), the way reference history is represented by the direction of the arrow in the figure, and it is defined that the entry to which the arrow is directed has been referred to before, and the direction of the arrow in FIG. The defined 6-bit information a, b, c, d, e, f is stored. When a replacement request is made, the way to which all arrows are directed is selected.

Now, consider a case where the address stored in the tag memory 102 and the search address input from the central processing unit match and the hit signal 12 is sent from the comparison circuit 106. FIG. 2A shows that the way is the most recently referenced way by reversing all the directions of the arrows directed to the ways corresponding to the hits, and the way for the LRU memory 104 is shown in FIG. Corresponding information without an invalid signal, for example, if way 0 is a hit, a = b = d = 0
Write.

On the other hand, consider a case where an invalid signal 11 for invalidating an entry is sent from the outside. Figure 2 (a)
2 indicates that the way is the earliest referenced way by reversing all the directions of the arrows going out of the corresponding way, and the LRU memory 104 has the invalid signal shown in FIG. Information to be written, for example, when way 0 is invalidated, a = b = d = 1 is written, and at the same time, information indicating that the valid memory 103 is an entry storing invalid data is written.

As a result of the above operation, when an entry is replaced, the entry most recently referred to by the LRU method is replaced, and if an invalid entry exists, the entry is replaced with priority, and the cache is cached. The use efficiency of the memory can be improved.

FIG. 3 is a circuit diagram showing a specific example of the LRU write control circuit 110. In FIG. 3, 110 is an LR
U write control circuit, 104 indicates a memory for LRU,
It corresponds to the numbers in FIG. Also, 111, 11
Reference numeral 2 indicates a way 0 indicating the match between the address stored in the tag memory 102 and the search address input from the outside.
A signal, a way 1 signal, 113 is a write signal 1 when there is no invalid signal, and 114 is a write signal 2 when there is an invalid signal. Although FIG. 3 shows the a-bit LRU write control circuit and the LRU memory out of the 6-bit LRU information, the other bits are also configured by the same circuit although the way signal input is different.

LRU memory 10 by hit signal 12
4 and the bit position written to the LRU memory 104 by the invalid signal 11 are equal, and each value has a negative relationship, the LRU write control circuit 110 has a simple circuit configuration as shown in FIG. can do.

[0020]

According to the present invention, it is possible to replace an invalid entry with priority by writing to the LRU storage means information that makes the entry the entry that was referred to the earliest when the entry is invalidated. When selecting an entry to be replaced, it is possible to output a selection signal only by the LRU method without requiring a control circuit that preferentially selects an entry in which invalid data is stored. A cache memory device that can be executed faster can be provided.

Further, the information which is written in the LRU storage means and which is the most recently referenced entry is in a negative relationship with the information which is written when the conventionally used data is referenced and which indicates the most recently referenced data. Another advantage is that the write control circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a cache memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining a reference history and an operation for rewriting the reference history in the cache memory device of FIG.

3 is a circuit diagram showing a specific example of an LRU write control circuit 110 of the cache memory device of FIG.

[Explanation of symbols]

101 ... Row decoder, 102 ... Tag memory, 103 ... Valid memory, 104 ... LRU memory, 105 ... Data memory, 106 ... Comparison circuit, 107 ... Selection circuit, 10
8 ... Column decoder, 110 ... LRU write control circuit, 1
1 ... invalid signal, 12 ... hit signal, 111 ... way 0 signal, 112 ... way 1 signal, 113 ... write signal 1, 114 ... write signal 2.

Claims (1)

[Claims] 1. A data memory comprising a plurality of entries for storing data, a tag memory comprising a plurality of entries corresponding to the storage data in the data memory and storing a part of the address, and the storage data in the data memory. And a valid memory for storing that the data is valid, and an LRU memory comprising a plurality of entries corresponding to the stored data of the data memory and storing reference information of the data. A cache memory device for replacing data by reference information of the LRU memory method, further comprising a control means for rewriting the reference information of the LRU memory in accordance with an invalid signal indicating that the data stored in the data memory becomes invalid. And a cache memory device.