JPH04268296A - Erasable type read out dedicated memory - Google Patents

Abstract

PURPOSE:To realize a high speed access by providing an EPROM in a cache memory which is operating at a high speed. CONSTITUTION:A multiplexer 1 selects either the data stored in an EPROM section 5 or the data stored in a data memory 2 as the data to be transmitted to the external through a data bus 11. The data memory 2 temporarily stores a portion of the data which are stored in the EPROM section 5 as a cache memory and when the data, read out from the host device, are located in the data memory 2, no read out from the EPROM section 5 takes place and instead the read out is conducted from the data memory 2. An address tag comparator 4 judges whether the newly read out data from the host device as the data stored in the memory 2 or not and if the data are not located in the memory 2, discard the mostly not read out data, which are located in the memory 2, and the data are stored.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to user programmable read only memories (PROMs), sometimes erasable user programmable read only memories (EPROMs).

0002

BACKGROUND OF THE INVENTION Conventional erasable user programmable read only memory (EPROM) has a slower operating speed compared to static random access memory (SRAM), and therefore computers using both EPROM and SRAM In systems etc., EPROM
In order to match the operating speed (access speed) of SRAM, "WAIT" is inserted into the SRAM access cycle to extend the cycle time.

0003

[Problems to be Solved by the Invention] As mentioned above, the access speed (access time) of the conventional EPROM is
Although it is slower than the access speed of RAM, it is faster than the access speed (cycle time) of the central processing unit (CPU), so it has not been a factor in increasing the processing speed of the entire system. However, in recent years, the cycle time of CPUs has been rapidly reduced. On the other hand, since the reduction in access time of EPROM is small, the cycle time of the CPU is shorter than the access time of EPROM. Therefore, when operating the EPROM, "WAIT" is inserted in the cycle time of the CPU. It has become necessary to extend the cycle time, which is a factor that degrades the overall system performance.

0004

The erasable read-only memory of the present invention includes a programmable read-only EPROM section that stores data in an erasable manner;
a data memory that operates at a higher speed than the EPROM section and stores part of the data stored in the EPROM section; an address tag that stores the address of the data stored in the data memory; When a read is received from the address tag, the address stored in the address tag is compared with the address sent from the host device, and when they match, the data in the data memory is sent to the data memory. and an address tag comparator that, when inputting an address of data that is not in the data memory, exchanges it with the address of the least read data in the data memory.

[0005]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a multiplexer 1 sends data to the outside via a data bus 11 to an EPRO
Select whether to use the data in the M section 5 or the data in the data memory 2. The data memory 2 serves as a cache memory and temporarily stores part of the data stored in the EPROM section 5. When data read from the host device is in the data memory 2, the data memory 2 is used as a cache memory. Data is read from this data memory 2 without reading from data memory 5. As data memory 2, its operating time is EPRO.
A device whose operation time is faster than that of the M section 5 is used. Therefore, the read data can be sent out at high speed.

The address tag 3 indicates at which address of the EPROM section 5 the data stored in the data memory 2 is located. The address tag comparator 4 compares the address input from the host device via the address bus 13 and the address of the address tag 3 to determine whether the data newly read from the host device is the data in the data memory 2 or not. Judging by comparing with
When the data is not in the data memory 2, the data is replaced by discarding the least read data in the data memory 2 and storing that data.

FIG. 2 is a block diagram showing an example of a computer system using the embodiment of FIG.

The difference between the system of FIG. 2 and the conventional system is that the EPROM 24 of this embodiment has different access times depending on whether data is stored in the data memory 2 or not. . Therefore, the address tag comparator 4 sends out the RDY signal 14 (see FIG. 1), which causes the MP
Notify U21 of the difference in access time. The ready control unit 27 notifies the MPU 21 of the difference in access time between the SRAM 23, EPROM 24, and I/O 25. When viewed from the outside, everything else is the same as the conventional system.

[0011]

[Effects of the Invention] As explained above, the EPRO of the present invention
M has the effect that even large-capacity EPROMs can be accessed at high speed by providing a cache memory inside the cache memory that operates at high speed, and can be achieved with fewer parts than providing a cache memory in an external circuit. Therefore, there is an effect that costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a computer system using the embodiment of FIG. 1;

[Explanation of symbols]

1 Multiplexer 2 Data memory 3 Address tag 4 Address tag comparator 5 EPROM section 11 Data bus 13 Address bus 14 RDY signal 21 MPU 23 SRAM 24 EPROM 25 I/O 27 Ready control section

Claims (1)

[Claims] 1. A programmable read-only EPROM section for erasably storing data;
a data memory that operates at a higher speed than the EPROM section and stores part of the data stored in the EPROM section; an address tag that stores the address of the data stored in the data memory; When a read is received from the address tag, the address stored in the address tag is compared with the address sent from the host device, and when they match, the data in the data memory is sent to the data memory. an address tag comparator for replacing an address of data that is not in the data memory with the address of the least read data in the data memory.