JPS615348A - Information processor - Google Patents

Abstract

PURPOSE:To improve the processing speed of an information processor including a horizontal microprocessor by providing said microprocessor that can issue a memory request during the interruption processing. CONSTITUTION:A suppressing instruction produced from a memory request is provided at a multiplexer state area 10-3. Decoding circuits 15-1 and 15-2 are connected to the suppressing area of the area 10-3 and a memory request state area 10-4, respectively. Both decoding circuits output logical high values, for example, in a suppression mode and a memory request mode. The output of the circuit 15-1 is inverted by an inverting circuit 15-3 and then set at a logical low value in a suppression mode to be used an input of an AND circuit 15-4. The other input of the circuit 15-4 is used as the output of the circuit 15-2. The setting action of a buffer register 12 is controlled by the output of the circuit 15-4. In such a way, the output of the circuit 15-4 is set at a low level with a memory request under interruption. Thus, rewrite of the address of the register 12 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device comprising a horizontal microprocessor in an information processing system comprising a horizontal microprocessor and a vertical microprocessor.

Information processing systems using horizontal microprocessors and vertical microprocessors are widely used to perform processing at high speed. This information processing system is shown in Fig. 2. A horizontal microprocessor 1 processes instructions in a memory 2 at high speed, and a vertical microprocessor 3 processes input/output devices. It manages the operations and horizontal processor operations.゛When the memory 2 is accessed during instruction processing in the horizontal microprocessor 1, if an address overflow or the like occurs, a micro-interrupt occurs. A silent interrupt is processed by interrupting to a fixed address according to the cause of each interrupt. Therefore, a buffer register is required to store the address of the microinstruction to be returned to after the interrupt processing is completed.

However, horizontal microprocessors generally set the addresses of the buffer registers mentioned above in response to memory requests. Therefore, if a memory request is made during interrupt processing, the address of the microinstruction to be returned to after the interrupt in the buffer register is destroyed. Therefore, the horizontal microprocessor cannot make a memory request during interrupt processing, and interrupt processing that requires a memory request must be requested to the vertical microprocessor 3 for processing. Therefore, the efficiency of horizontal microprocessors is poor, and improvements are desired.

[Conventional technique]

A conventional horizontal microprocessor will be explained using FIG. FIG. 3 is a microinstruction sequence circuit diagram of a horizontal microprocessor. Microinstruction register 10
stores a microinstruction to be retrieved from the control storage section (control storage) 11, and as shown in the figure, it has a next address storage area 10-1, a branch instruction area 10-2, a multiplexer state area 10-3, and a memory request state area. 10-4.

The buffer register 12 is a memory request status area 10.
It functions to store the address that is input when -4 is in the request state. The multiplexer 13 is
The input is selected by the multiplexer state area 10-3. The fixed address generation circuit 14 has a function of generating a fixed address for each cause of micro-interrupt generation.

The operation will be explained below. A microinstruction is set in the microinstruction register 10 from the control storage unit 11 . Areas 10-2 to 10-4 except for the next address storage area 10-1 of the microinstruction register 10 control various hardware. That is, the multiplexer state area 10-3 controls the multiplexer 13, and the memory request state area 10-4 controls the multiplexer 13.
controls address storage in the buffer register 12. The next address in the next address storage area 10-1 is the multiplexer 1
3, the microinstructions at the next address are sequentially called from the control storage unit 11 to the microinstruction register 10 for processing.

As described above, the conventional device is configured from the viewpoint that the occurrence of an interrupt is always a memory request, and when an interrupt occurrence cause 14-1 occurs, the fixed address generation circuit 14 outputs a fixed address for each cause. . At this time, multiplexer 13 outputs a fixed address and searches the control storage section. Further, the buffer register 12 outputs the address of the instruction to be executed next after the instruction that caused the interrupt, and when the interrupt processing is completed, the multiplexer 13 outputs the address of the buffer register 12 and outputs the return address from the interrupt. Therefore, if a memory request is made while an interrupt is occurring, the return address will be destroyed.

[Problem that the invention seeks to solve]

The above configuration has a problem in that a memory request cannot be made during an interrupt, and processing is requested to the vertical microprocessor, resulting in poor efficiency of the horizontal microprocessor.

[Means for solving problems]

The present invention provides an information processing device that solves the above-mentioned problems, and its means include a buffer register that stores a return address from an interrupt, and sets the buffer register by a memory request of a microinstruction. In a horizontal microprocessor, an information processing device stores an instruction for inhibiting the set outside the memory request area of a microinstruction register of the horizontal microprocessor, and inhibits the set by the memory request by the inhibit instruction. It will be done.

[Effect]

This prevents the buffer register that stores the return address from an interrupt from being set by a memory request outside the memory request area of the microinstruction register of the horizontal microprocessor.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of essential parts of an embodiment of the present invention.

Note that the same parts are denoted by the same reference numerals throughout the figures.

The only difference from the present embodiment in FIG. 3 is the portion surrounded by a dashed line in the figure, and this portion will be explained below.

One of the features of the present invention is that a memory request inhibit instruction is provided in the multiplexer state area 10-3.

That is, in the memory request state area 10-4, there are multiple factors that make a request, such as the first operand, second operand, read, and write commands, and it is not possible to attach set permission and set inhibition to each of these multiple factors. Since this not only becomes more complicated, but also increases the required memory request status area 10-4, a 1-bit inhibition area is provided in the multiplexer status area 10-3.

A decoding circuit 15-1 is placed in the inhibition area of the multiplexer state area 10-3, and a decoding circuit 1 is placed in the memory request status area.
5-2 is connected so that each decoding circuit 15-1, 15-2 outputs, for example, a logical value of "1°" in the inhibit state and the memory request state.

The output of the decoding circuit 15-1 is inverted by the inverting circuit 15-3.
When in the inhibited state, the AND circuit 15-4 is inverted with a logical value of "0", and the other inputs are outputted from the decoding circuit 15-20 and buffered by the output of the AND circuit 15-4. Controls the setting operation of the register 12.

That is, when a memory request is made while an interrupt is occurring, the inhibit area is set to a logic value "1" in the inhibit area of the other microinstruction register that is processing the interrupt, and the AND circuit '15-4 is processed by the memory request during the interrupt. Set the output to logical value “0”
By doing so, address rewriting of the buffer register 12 due to a memory request is suppressed.

〔Effect of the invention〕

As described above, according to the present invention, a horizontal microprocessor that can make a memory request during interrupt processing is provided, which is highly effective in improving the processing speed of an information processing device including a horizontal microprocessor.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of an embodiment of the present invention, Fig. 2 is a block diagram of an information processing system of a horizontal microprocessor, and Fig. 3 is a microinstruction sequence circuit diagram of a conventional horizontal microprocessor. be. In the figure, 1 is a horizontal microprocessor, 3 is a vertical microprocessor, 10 is a microinstruction register,
12 each indicates a buffer register. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a horizontal microprocessor that has a buffer register that stores a return address from an interrupt and sets the buffer register by a memory request of a microinstruction, the set is placed outside the memory request area of the microinstruction register of the horizontal microprocessor. An information processing device characterized in that an information processing device stores an instruction for inhibiting the memory request, and the inhibiting instruction inhibits the setting caused by the memory request.