JPH02285441A - Cache controller - Google Patents

Abstract

PURPOSE:To hold data with high efficiency by using a write inhibiting bit. CONSTITUTION:A write inhibiting register 1 holds a write inhibiting bit to show whether a writing action is granted or not to the bit which is selected with the set address input of an input address and outputs the information on the write inhibiting bit as a write inhibiting signal 102. A write control circuit 2 outputs a write signal 108 to show whether the data should be written into a cache data memory 3 for not with the use of the signal 102, a hit signal 107, and a write requesting signal 106. Thus no data is written with the bit that is designated by the signal 102 even though the signal 106 and then the signal 107 are inputted. Consequently, the bit data is not rewritten and held in the memory 3 and the availability of the cache data is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for controlling data retention in a data memory of a cache.

[Prior Art] Conventionally, cache data memory uses a central processing unit (C
Data that has not been accessed recently by a PU (PU) is replaced to preserve recently accessed data, regardless of whether this data will be accessed in the near future. It was always stored.

[Problems to be Solved by the Invention] In the conventional cache data memory described above, data that has not been accessed recently by the CPU is
Regardless of whether this data is data that will be accessed in the near future, the data is replaced in order to always store recently accessed data, so even if the possibility of access is high, the access frequency is Data with a low value is not retained in the cache. For this reason, there is a drawback that the extremely limited memory area of the cache data memory is not utilized effectively.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a cache control device that can achieve effective utilization of cache data memory.

[Differences between the invention and the prior art] The conventional cache memory described above always stores data that has not been accessed recently by the CPU, regardless of whether or not this data will be accessed in the near future. In order to maintain the data, the data is replaced.
By using the write protection bit, the present invention allows data to be retained without being rewritten if it is known that it will be accessed in the near future, thereby preventing meaningless replacement of data in data memory. The difference is that data can be stored efficiently.

That is, in the present invention, a certain area of the cache data memory is converted into a ROM using a write protection bit, and the area to be converted into a ROM can be arbitrarily changed by specifying the write protection bit.

[Means for Solving the Problems] A cache control device of the present invention includes a write prevention register that stores a write prevention bit indicating whether or not to permit data writing to a data memory of a cache, and a write prevention register that stores a write prevention bit indicating whether or not to permit data writing to a data memory of a cache. The present invention is characterized in that it includes a write control circuit that determines whether or not to write based on bit information of a write protection register.

A more specific preferred embodiment of the present invention includes a write prevention register that stores a write prevention bit indicating whether or not data is permitted to be written, and a write prevention signal output from the write prevention register and a cache external a write control circuit that determines whether or not to execute writing to the data memory of the cache based on a write request signal input from the write request signal and a hit signal output from the hit determination circuit; and a write signal output from the write control circuit. A cache data memory that is accessed by an address, a hit determination circuit that determines whether it is a cache hit or a cache miss based on the tag address of the tag memory and the tag address of the input address, and the tag memory that stores the tag address. and a valid register that stores a valid bit indicating whether the data is valid or not.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a drawing showing a cache control device according to an embodiment of the present invention, and only the portions related to the present invention are shown in this figure.

The write prevention register 1 holds a write prevention bit indicating whether or not to permit writing to the bit selected by the set address input of the input address, and outputs this write prevention bit information as a write prevention signal 102.

Note that setting of the write protection bit in the write protection register 1 is performed by a write protection set signal 101.

The write control circuit 2 uses a write prevention signal 102, a hit signal 107 indicating whether it is a cache hit or a cache miss, and a write request signal 106 indicating a write request from outside the cache control device to write data to the cache data memory 3. It outputs a write signal 108 indicating whether or not to execute data writing, and also outputs a write error signal 105 indicating that a write request has been made to an area where writing is not permitted.

The valid register 6 holds a valid bit indicating whether or not data is valid in the bit selected by the set address input, and outputs this valid bit information as a valid signal 104. The valid bit is set in the valid register 6 by a valid set signal 1.degree.3. The hit determination circuit 4 determines whether it is a cache hit or a cache miss based on the tag address signal 111, the tag address input 109 of the input address, and the valid signal 104, and outputs a hit signal 107.

The tag memory 5 stores the tag address of the cache data stored in the cache data memory 3,
The tag address accessed by the set address input 110 is output to the tag address signal 111. The cache data memory 3 stores cache data, and writes data 112 to the data selected by the set address manual 110 in response to a write signal 108.

That is, according to the above configuration, the write request signal 106
is input and the hit signal 107 is input, data is not written to the bit specified by the write prevention signal 102, and the data of the bit is retained in the data memory 3 without being rewritten. be done.

FIG. 2 is a diagram showing a cache control device according to another embodiment of the present invention. In this embodiment, the write protection signal 201 from the write protection register 1 is not input to the write control circuit 2 as in the previous embodiment, but is input to the hit determination circuit 11 and the write error determination circuit 12. The hit determination circuit 11 determines whether there is a cache hit or a cache miss and at the same time determines whether writing is permitted based on the write prevention signal 201, and sends this determination result to the access control circuit 204 and the write error determination circuit using the hit signal 204. Notify 12. The write error determination circuit 12 detects the write prevention signal 201
Based on the hit signal 204 and the access request signal 202, it is determined whether or not this is a write request to cache data for which writing is not permitted, and the result of this determination is output as a write error signal 205. Access control circuit 10
outputs an access signal 203 to the data memory 3 based on an external access request signal 202 in cases other than requests for writing to cache data for which writing is not permitted.

Therefore, in this embodiment as well, cache data to which access is not permitted is not rewritten, and the data is held in the data memory 3.

In this embodiment, the write error determination circuit 1 generates the access signal 203 at the same time as the access control circuit 10 generates the access signal 203.
Since the write error signal 205 is generated in step 2 and notified to the outside, there is an advantage that the speed of the external circuit can be increased.

[Effects of the Invention] As explained above, the present invention prevents a portion of the cache data memory from RO by providing a write protection register.
Since it can be used as M, the utilization efficiency of cache data can be improved without requiring an external ROM. Further, there is an effect that the area to be converted into ROM can be increased or decreased freely by the write prevention set signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a cache control device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a cache control device according to another embodiment of the invention. 1- ・ -・ ・ Meeting φ 2 ・ ・ ・ ・ ・ −・ 3 ・ ・ φ e φ Order 4.11φ1111 Building 5 ・ ・ ・ ・ ・ ・ 6・ ・ Service ・ ・ ・ 10- φ ・ φ No.・ 12... Fist number... 101- Life ・ φ and 102. 201st number 103 ・ ・ Number −・ 10/One fight-・φ 105, 205 φ 106 ・ ・ ・ ・ 107, 204- 108#Φ Reikai・ 203 φ Tsubo Shima ・ War 109... No. 110 φ φ −・ Humiliation 111 φφφ No. Φ ・Write protection register, ・Write control circuit, ・Cache data memory ・Hit judgment circuit, ・Tag memory, ・Valid register, ・Access control circuit, ・Write error determination circuit, ・Write protection set signal, ・Write prevention signal, ・Valid set signal, ・Valid signal, ・Write error signal, ・Write request signal, ・Hit signal, ・Write Signals: ・Access signal, ・Tag address input signal, ・Set address input signal, ・Tag address signal, 112. .Data, 202. .Access request signal.

Claims (1)

[Claims] A write-protection register that stores a write-protection bit that indicates whether or not data writing to the data memory of the cache is permitted, and a write control circuit that determines whether data can be written to the data memory based on the bit information of the write-protection register. A cache control device comprising: