JPS638849A - Chche memory control system - Google Patents

Abstract

PURPOSE:To contrive coincidence of a main storage device with a cache memory by invalidating a block when a self-processing device having the cache memory is accessed with a test and set to the semaphore byte of the main storage device and the cache memory is hit. CONSTITUTION:Plural processing units 11-1n are connected through a memory bus 3 to a common main storage device 2, respective processing devices are composed of a cache memory and the main storage device 2 is composed of a common area and a semaphore byte corresponding to it. When a self- processing unit is accessed by the test and set to the semaphore byte of the main storage device 2 and the cache memory is hit, the block is invalidated. thus, since the cache memory of respective processing units is hit, the main storage device 2 and the cache memory can be agreed.

Description

[Detailed Description of the Invention] [Summary] This is a cache memory control method in which when a self-processing device having a cache memory accesses the main memory by test-and-set, if the cache memory is hit, other processing devices When a write access is hit, the corresponding block is invalidated using the same hardware and operation.

[Industrial application field]

The present invention is applicable to a system in which a plurality of processing units connected via a bus use a common main storage device (Fig. 1).
, relates to a cache memory control method when the cache memory of its own processing device is hit when accessing the semaphore byte of the main storage device by test-and-set.

[Conventional technology]

In an information processing system in which multiple processing units are connected to a common main storage unit via a bus (Figure 1), a specific common area provided on the main storage unit is generally used for communication between these processing units ( Figure 4).

Then, a corresponding semaphore byte is provided in the same main memory to indicate whether or not this common area is in use (Figure 4), and when a usage request occurs, the corresponding common area is accessed by accessing this semaphore byte. The company checks whether there is a right to use the site and acquires the right to use it.

Conventionally, the most effective means for a processing unit to access a semaphore byte in main memory is during a single memory bus acquisition by test-and-set.

Here, the test and set is an instruction to issue an address, read data, and write data during one memory bus acquisition.

[Problem that the invention seeks to solve]

As described above, conventionally, access to the semaphore byte by test and set was performed in one operation.

However, recently, in order to meet the demand for faster information processing systems, each processing device is equipped with a cache memory that stores a copy of the data in the main storage device, thereby enabling high-speed access.

In this way, in an information processing system in which each processing unit is equipped with a cache memory and connected to a main storage unit, when a certain processing unit accesses a semaphore byte in the main storage unit by test and set, this access The block containing the semaphore byte may already exist in the cache memory and the valid flag may be on.

In such a case, there is a problem in that it is extremely difficult to try to match the main storage device and the cache memory because the cache memory is hinted.

[Means for solving problems]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to invalidate the hinted block if the cache memory of its own processing device is hit when accessing a semaphore byte in a main memory by test-and-set.

Therefore, multiple processing units are connected to a common main storage device via a memory bus, each processing unit is configured with a cache memory, and the main storage device is configured with a common area and its corresponding semaphore bytes. When the device accesses the semaphore byte in the main memory by test and set, if the cache memory gives a hint, the block is invalidated.

[For production]

As described above, when a self-processing device having a cache memory accesses a semaphore byte in a main storage device by test-and-set, the block when the cache memory is hit can be invalidated.

Therefore, the conventional problem that it is difficult to unify the main memory and the cache memory because the cache memory of each processing unit is hit is eliminated.

〔Example〕

The invention will now be explained by way of example with reference to the accompanying drawings.

FIG. 1 is a system configuration diagram according to the present invention.

The information processing system shown in FIG.
, 12...in are connected to a common main storage device 2 via a memory bus 3, and each processing device is composed of a processing section, a control section, and a cache memory.

FIG. 2 is a detailed diagram of each of the processing devices described above, and shows the processing device 11 as an example. Other processing equipment 12
, 13...1n also have the same configuration.

The processing device 11 includes a processing section 111, a control section 112, and a cache memory 113.

The processing unit 111 is connected to the memory bus 3 via a control unit 112, and a cache memory 113 is connected to the control unit 112.

Furthermore, the cache memory 113 is a buffer memory 1131.
, a directory 1132 and a comparison circuit 1133.

The buffer memory 1131 holds a copy of the data in the main storage device 2, the directory 1132 holds an address tag indicating the correspondence between the buffer memory 1131 and the main storage device 2, and the comparison circuit 1133 receives a copy of the data from the control unit 112. The address and the tag of the directory 1132 are compared.

FIG. 3 shows an invalidation instruction circuit, which is provided inside the control unit 112, and includes a Nant gate 1121 to which a memory bus acquisition signal and an inverted test and set signal are input, and the output and invalidation timing of the Nant gate. It consists of an AND gate 1122 into which signals and control signals are input.

Hereinafter, the present invention having the above configuration will be explained in detail.

(1) Normal operation.

In response to an access request from the processing unit 111 to the main storage device 2, the cache memory 113 normally compares the address notified from the control unit 112 and the tag of the directory 1132 in the comparison circuit 1133, and compares the comparison result. The control unit 112 is notified by the control signal COM.

■ An access request from the processing unit 111 to the main storage device 2 is
Behavior in case of lead.

If the comparison result is a failure, that is, if the cache memory 1131 is hit, the set of output data of the buffer 1 memory 1131 that has the same addressing as the tag of the directory 1132 is selected by the control signal COM. is sent to the processing unit 111 via the control unit 112.

At this time, the control unit 112 suppresses the acquisition request for the memory bus 3 using the control signal COM.

When the control signal COM indicates a miss, the control unit 112 acquires the memory bus 3 and reads the block containing the requested data from the main storage device 2. Furthermore, the control unit 112 replenishes blocks in the buffer memory 1131 and writes tags in the directory 1132, respectively, and sends request data to the processing unit 1.

This allows the processing unit 111 to read predetermined request data.

■ An access request from the processing unit 111 to the main storage device 2 is
Behavior for lights.

If the comparison result is a failure and the cache memo January 131 is a hit, the hit entry in the buffer memory 1131 is rewritten. At the same time, the control unit 112 controls the memory bus 3
By acquiring , writing to the main memory device 2 is performed.

If there is a miss, only writing to the main storage device 2 is performed.

(2) Further, the control unit 112 constantly monitors the memory bus 3, so that access requests to the main storage device 2 of other processing devices 12, 13-1n are transmitted to the cache memory 1 of the own processing device 11.
Based on the control signal COM, it is determined whether or not the request is for writing to a block whose address matches the address of the main memory 2 held in the main memory 13.

If it is a write hit, the control unit 112 outputs the control signal INV.
By sending this, the tag of the hinted block in the directory 1132 is instructed to be invalidated (FIG. 3).

(2) Invalidation processing operation when the cache memo 132 of the own processing device 11 gives a hint when accessing the semaphore byte of the main storage device 2 by test and set.

FIG. 4 is a block diagram of the main memory device 2 used in the present invention, in which semaphore bytes 21S, 22S, -2nS are provided corresponding to common areas 21, 22-2n, respectively. By accessing this semaphore byte, it is confirmed whether or not the right to use a predetermined common area is available, and the right to use the same is acquired.

Below, when accessing test and set, the self-processing device 11
The operation when the cache memory 113 of is hit is as follows.
This will be explained based on FIG.

In the operation explanatory diagram of FIG. 5, ``address ADR and read data RD sent to the memory bus 3.''

Write data WD (■) and bus request signal (■)
), test and set instruction (■), and memory bus 3
The address launch instruction signal (■) issued to
Time charts are drawn for M (■), the invalidation timing signal (■), and the control signal INV (■) for invalidating the hit block. In the figure, the time area between solid lines is the memory bus acquisition period (■).

While monitoring the acquired memory bus 3, the own processing device 11 uses the control signal COM to control other processing devices 12--1.
If it is determined that n is a write access hit,
At time T when the write data WD is output to the memory bus 3, an invalidation timing signal is sent (■ in FIG. 5). Therefore, the AND gate 1122 of the invalidation instruction circuit (FIG. 3)
A control signal INV is sent from the directory 1132 to the directory 1132 (FIG. 2), instructing the directory 1132 to invalidate the tag of the hit block. That is, the timing of this invalidation is the same as the invalidation timing of (1) above.

In other words, the present invention realizes a means for invalidating the internal memory when the own processing device accesses the memory by using a monitoring function and an invalidation function when accessing by another processing device.

Note that, as a matter of course, if the test and set results in a hit in the cache memory of another processing device 12...1n, its own tag is invalidated as a write hint.

〔Effect of the invention〕

As described above, when a self-processing device having a cache memory accesses a semaphore byte in a main storage device by test-and-set, the block when the cache memory is hit can be invalidated.

Therefore, the conventional problem that it is difficult to match the main storage device and the cache memory because the cache memory of each processing unit is hinted is eliminated.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram according to the present invention, FIG. 2 is a diagram showing an embodiment of a processing device, FIG. 3 is a diagram showing an embodiment of an invalidation instruction circuit according to the present invention, and FIG. 4 is a diagram showing an embodiment of a processing device according to the present invention. FIG. 5, which is a block diagram of the storage device, is an explanatory diagram of the operation of the present invention. 2... Main storage device, 3... Memory bus, 1
1, 12--1n... Processing device, 111... Processing unit, 112... Control unit, 113... Cache memory, 1131... Buffer memory, 1132... Directory, 1133...・Comparison circuit.

Claims (1)

[Claims] 1. A plurality of processing devices are connected to a common main storage device via a memory bus, and each processing device is configured with a cache memory, and the main storage device is configured to have a common area and a semaphore byte corresponding to the common area. A cache memory control method comprising the following: When a self-processing device accesses a semaphore byte of a main storage device by test-and-set, if the cache memory is hit, the block is invalidated. 2. The invalidation of the block is performed using exactly the same hardware and operation as when a write access of another processing device hits while the own processing device is monitoring the memory bus. The cache memory control method described in scope 1.