JPS556632A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS556632A
JPS556632A JP7905278A JP7905278A JPS556632A JP S556632 A JPS556632 A JP S556632A JP 7905278 A JP7905278 A JP 7905278A JP 7905278 A JP7905278 A JP 7905278A JP S556632 A JPS556632 A JP S556632A
Authority
JP
Japan
Prior art keywords
cpu
memory
main memory
memory access
operands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7905278A
Other languages
Japanese (ja)
Other versions
JPS6112581B2 (en
Inventor
Tadao Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7905278A priority Critical patent/JPS556632A/en
Publication of JPS556632A publication Critical patent/JPS556632A/en
Publication of JPS6112581B2 publication Critical patent/JPS6112581B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To improve the performance of a system by making it unneeded to lock a main memory by registering blocks of test and set instructions with operands newritten to a cash memory.
CONSTITUTION: Processors CPU1 and CPU2 and channel processor CHP attain access to main common memory MM via memory access controller MCU. Here, CPU1 and CPU2 are equipped with cash memories CM1 and CM2 respectively, which control the rewriting to the main memory by swapping. Namely, blocks of test and set instructions with their operands rewritten to memories CM1 and CM2 are registered to eliminate the need for locking the main memory MM. Consequently, the performance of the system can be improved.
COPYRIGHT: (C)1980,JPO&Japio
JP7905278A 1978-06-29 1978-06-29 Memory access control system Granted JPS556632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7905278A JPS556632A (en) 1978-06-29 1978-06-29 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7905278A JPS556632A (en) 1978-06-29 1978-06-29 Memory access control system

Publications (2)

Publication Number Publication Date
JPS556632A true JPS556632A (en) 1980-01-18
JPS6112581B2 JPS6112581B2 (en) 1986-04-09

Family

ID=13679116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7905278A Granted JPS556632A (en) 1978-06-29 1978-06-29 Memory access control system

Country Status (1)

Country Link
JP (1) JPS556632A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718778A (en) * 1980-07-08 1982-01-30 Mitsubishi Electric Corp Liquid crystal composition
JPS638849A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd Chche memory control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718778A (en) * 1980-07-08 1982-01-30 Mitsubishi Electric Corp Liquid crystal composition
JPS621635B2 (en) * 1980-07-08 1987-01-14 Mitsubishi Electric Corp
JPS638849A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd Chche memory control system

Also Published As

Publication number Publication date
JPS6112581B2 (en) 1986-04-09

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