JPS57178553A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS57178553A
JPS57178553A JP6366981A JP6366981A JPS57178553A JP S57178553 A JPS57178553 A JP S57178553A JP 6366981 A JP6366981 A JP 6366981A JP 6366981 A JP6366981 A JP 6366981A JP S57178553 A JPS57178553 A JP S57178553A
Authority
JP
Japan
Prior art keywords
processor
exclusive execution
arbiter
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6366981A
Other languages
Japanese (ja)
Other versions
JPS6326907B2 (en
Inventor
Kazuharu Itakura
Masatoshi Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6366981A priority Critical patent/JPS57178553A/en
Publication of JPS57178553A publication Critical patent/JPS57178553A/en
Publication of JPS6326907B2 publication Critical patent/JPS6326907B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To use a common memory efficiently by supplying a permit signal for exclusive execution from an exclusive execution arbiter to only one processor, and executing only an unseparable operation part exclusively. CONSTITUTION:For example, when an exclusive execution request signal 7 is outputted from a processor 0 to an exclusive execution arbiter 9, a gate 27 inhibits the passing of a clock signal 18 in the processor 0, so a microprogram counter 22 stops operation. Then when the signal 7 is accepted by the arbiter 9, an exclusive execution permit signal 8 is outputted to the processor 0. Consequently, the output of a gate 26 goes down to ''0'' to reset an FF25, and the clock signal of the gate 27 is validated, allowing an advance in a microprogram. Once the exclusive execution by the processor 0 and arbiter 9 ends, an exclusive execution request signal by another processor ia accepted by the arbiter 9. Therefore, a common memory 6 is not used exclusively for unseparable operation, but is used effectively.
JP6366981A 1981-04-27 1981-04-27 Multiprocessor system Granted JPS57178553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6366981A JPS57178553A (en) 1981-04-27 1981-04-27 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6366981A JPS57178553A (en) 1981-04-27 1981-04-27 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPS57178553A true JPS57178553A (en) 1982-11-02
JPS6326907B2 JPS6326907B2 (en) 1988-06-01

Family

ID=13235980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6366981A Granted JPS57178553A (en) 1981-04-27 1981-04-27 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS57178553A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121468A (en) * 1982-01-13 1983-07-19 Matsushita Electric Ind Co Ltd Multiprocessor device
JPS60169969A (en) * 1984-02-15 1985-09-03 Fuji Electric Co Ltd Multiprocessor system
JPS60243763A (en) * 1984-05-17 1985-12-03 Fuji Electric Co Ltd Dual port memory control circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0317370Y2 (en) * 1988-05-13 1991-04-12
JPH02108204U (en) * 1989-02-14 1990-08-28

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103663A (en) * 1979-01-31 1980-08-08 Nissin Electric Co Ltd Micro computer composite unit
JPS5734263A (en) * 1980-08-04 1982-02-24 Kokusai Electric Co Ltd Simple multiprocessor system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55103663A (en) * 1979-01-31 1980-08-08 Nissin Electric Co Ltd Micro computer composite unit
JPS5734263A (en) * 1980-08-04 1982-02-24 Kokusai Electric Co Ltd Simple multiprocessor system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121468A (en) * 1982-01-13 1983-07-19 Matsushita Electric Ind Co Ltd Multiprocessor device
JPS60169969A (en) * 1984-02-15 1985-09-03 Fuji Electric Co Ltd Multiprocessor system
JPS60243763A (en) * 1984-05-17 1985-12-03 Fuji Electric Co Ltd Dual port memory control circuit

Also Published As

Publication number Publication date
JPS6326907B2 (en) 1988-06-01

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