JPS5624656A - Debug verifying device - Google Patents

Debug verifying device

Info

Publication number
JPS5624656A
JPS5624656A JP10010179A JP10010179A JPS5624656A JP S5624656 A JPS5624656 A JP S5624656A JP 10010179 A JP10010179 A JP 10010179A JP 10010179 A JP10010179 A JP 10010179A JP S5624656 A JPS5624656 A JP S5624656A
Authority
JP
Japan
Prior art keywords
debug
program
cpu1
cpu
informed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10010179A
Other languages
Japanese (ja)
Inventor
Shunsaku Fukunishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10010179A priority Critical patent/JPS5624656A/en
Publication of JPS5624656A publication Critical patent/JPS5624656A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the debug manpowers by carrying out the debug by connecting to the debug system having the same function as the existing system.
CONSTITUTION: In the conventional system CPU1, the software to OS control function and the processing program is provided in the main memory 1'. In the newly developed system CPU2, the program for realizing the same function as CPU1 is accommodated in the main memory 2'. In the memory 2', a part of OS control or a part of the processing program is replaced by the microprogram 4. The debug verifying device 3 is connected to CPU1, 2 and both CPU are respectively controlled so as to perform the program. In the respective programs the check point corresponding to the program is disposed, the check point to be compared is informed to the device 3 and the order to be stopped is disposed at CPU sides 1, 2. In the device 3, the information from both CPU check points is compared and if it is not coincided, it is informed.
COPYRIGHT: (C)1981,JPO&Japio
JP10010179A 1979-08-06 1979-08-06 Debug verifying device Pending JPS5624656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10010179A JPS5624656A (en) 1979-08-06 1979-08-06 Debug verifying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10010179A JPS5624656A (en) 1979-08-06 1979-08-06 Debug verifying device

Publications (1)

Publication Number Publication Date
JPS5624656A true JPS5624656A (en) 1981-03-09

Family

ID=14264997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10010179A Pending JPS5624656A (en) 1979-08-06 1979-08-06 Debug verifying device

Country Status (1)

Country Link
JP (1) JPS5624656A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61165141A (en) * 1985-01-17 1986-07-25 Toshiba Corp Control device of backup computer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61165141A (en) * 1985-01-17 1986-07-25 Toshiba Corp Control device of backup computer

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