JPS5458324A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS5458324A JPS5458324A JP12451777A JP12451777A JPS5458324A JP S5458324 A JPS5458324 A JP S5458324A JP 12451777 A JP12451777 A JP 12451777A JP 12451777 A JP12451777 A JP 12451777A JP S5458324 A JPS5458324 A JP S5458324A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- key
- protect
- protection
- artificial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Storage Device Security (AREA)
Abstract
PURPOSE: To enable to execute the operation of memory protect even between the emulated progams, by operating the memory protection exception circuit, if the result of comparison between the key value from the memory protect key memory unit and that of the artificial protection ley is not in accordance with a given law.
CONSTITUTION: The memory protection key memory unit 1 atores the memory protection key desitnated and fed from the line 2, and the load PSW instrucion altering the program conditional word is fed to the artificial protection key register 7 through the line 6, and the information under the execution of the emulated program is fed to the latch 14 through the line 13. If the artificial protection key is detected 10 as it is not 0, the key value from the unit 1 and that of the artificial protectin key are compared 5, and if the result is not in accordance with a given law and the request to the main memory unit sores the information, the memory protect exemption circuit 16 operates a specific microprogram, enabling to perform the memory protect operation between the emulated programs for the instructions requirring to operate the memory protect key and protect keys
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12451777A JPS5458324A (en) | 1977-10-19 | 1977-10-19 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12451777A JPS5458324A (en) | 1977-10-19 | 1977-10-19 | Information processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5458324A true JPS5458324A (en) | 1979-05-11 |
JPS6118224B2 JPS6118224B2 (en) | 1986-05-12 |
Family
ID=14887427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12451777A Granted JPS5458324A (en) | 1977-10-19 | 1977-10-19 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5458324A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6273333A (en) * | 1985-09-26 | 1987-04-04 | Nec Corp | Emulation control system |
-
1977
- 1977-10-19 JP JP12451777A patent/JPS5458324A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6273333A (en) * | 1985-09-26 | 1987-04-04 | Nec Corp | Emulation control system |
JPH0564375B2 (en) * | 1985-09-26 | 1993-09-14 | Nippon Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS6118224B2 (en) | 1986-05-12 |
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