JPS5452951A - Processor - Google Patents

Processor

Info

Publication number
JPS5452951A
JPS5452951A JP11904277A JP11904277A JPS5452951A JP S5452951 A JPS5452951 A JP S5452951A JP 11904277 A JP11904277 A JP 11904277A JP 11904277 A JP11904277 A JP 11904277A JP S5452951 A JPS5452951 A JP S5452951A
Authority
JP
Japan
Prior art keywords
register
order
address
improper
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11904277A
Other languages
Japanese (ja)
Inventor
Takashi Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11904277A priority Critical patent/JPS5452951A/en
Publication of JPS5452951A publication Critical patent/JPS5452951A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To stop the program runaway be suppling previously the improper order to the idle address of the memory and then reading the improper order when the program has runaway and comes to the idle address.
CONSTITUTION: The order designated by address register 1 ia read out through memory 2 and then supplied to order register 3. The order is decoded and executed at execution circuit 4, and the address to be executed next is supplied to register 1. In this case, if the parity error of register 3 is detceted through parity check circuit 5, the input of the address register is not gated via gate 6. Furthermore, when the contents of the order register is decoded through circuit 4 as the improper order, the input of the address register is not gated via gate 7. Accordingly, the program runaway can be prevented by supplying previously the improper oeder to the idle address within memory 2
COPYRIGHT: (C)1979,JPO&Japio
JP11904277A 1977-10-05 1977-10-05 Processor Pending JPS5452951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11904277A JPS5452951A (en) 1977-10-05 1977-10-05 Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11904277A JPS5452951A (en) 1977-10-05 1977-10-05 Processor

Publications (1)

Publication Number Publication Date
JPS5452951A true JPS5452951A (en) 1979-04-25

Family

ID=14751494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11904277A Pending JPS5452951A (en) 1977-10-05 1977-10-05 Processor

Country Status (1)

Country Link
JP (1) JPS5452951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61118833A (en) * 1984-11-14 1986-06-06 Fujitsu Ltd Audio response unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61118833A (en) * 1984-11-14 1986-06-06 Fujitsu Ltd Audio response unit

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