JPS55119750A - Processor providing test address function - Google Patents

Processor providing test address function

Info

Publication number
JPS55119750A
JPS55119750A JP2739879A JP2739879A JPS55119750A JP S55119750 A JPS55119750 A JP S55119750A JP 2739879 A JP2739879 A JP 2739879A JP 2739879 A JP2739879 A JP 2739879A JP S55119750 A JPS55119750 A JP S55119750A
Authority
JP
Japan
Prior art keywords
address
memory
interruption
test address
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2739879A
Other languages
Japanese (ja)
Inventor
Yoshiji Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP2739879A priority Critical patent/JPS55119750A/en
Publication of JPS55119750A publication Critical patent/JPS55119750A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To perform the alteration of address to be tested dynamically, by comparing the content between the address and test address register when CPU accesses the memory, and producing the interruption signal based on the coincidence detection signal.
CONSTITUTION: In the processor CPU1 operated according to the stored program, CPU1 operates according to the program stored in the memory 2. Further, the content of the test address register 3 settable with program and the address when CPU1 accesses the memory 2 are sequentially compared at the coincidence detection circuit 4. As a result, when the circuit 4 detects the coincidence, the coincidence detection signal is produced and the interruption signal is produced with the interruption to the interruption request circuit 5 based on the detection signal. Thus, it can be applied to rewriting-disenable memory, the restoration of the instruction is not necessary, and the alteration of the address to be tested can be made dynamically.
COPYRIGHT: (C)1980,JPO&Japio
JP2739879A 1979-03-09 1979-03-09 Processor providing test address function Pending JPS55119750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2739879A JPS55119750A (en) 1979-03-09 1979-03-09 Processor providing test address function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2739879A JPS55119750A (en) 1979-03-09 1979-03-09 Processor providing test address function

Publications (1)

Publication Number Publication Date
JPS55119750A true JPS55119750A (en) 1980-09-13

Family

ID=12219947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2739879A Pending JPS55119750A (en) 1979-03-09 1979-03-09 Processor providing test address function

Country Status (1)

Country Link
JP (1) JPS55119750A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856051A (en) * 1981-09-29 1983-04-02 Fujitsu Ltd Address comparison system by access interruption
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPH02140839A (en) * 1988-11-22 1990-05-30 Nec Corp Processing system for brake point
JPH0424836A (en) * 1990-05-18 1992-01-28 Fujitsu Ltd Microprocessor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856051A (en) * 1981-09-29 1983-04-02 Fujitsu Ltd Address comparison system by access interruption
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPH02140839A (en) * 1988-11-22 1990-05-30 Nec Corp Processing system for brake point
JPH0424836A (en) * 1990-05-18 1992-01-28 Fujitsu Ltd Microprocessor

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