JPS55154638A - Error processing system - Google Patents

Error processing system

Info

Publication number
JPS55154638A
JPS55154638A JP6128179A JP6128179A JPS55154638A JP S55154638 A JPS55154638 A JP S55154638A JP 6128179 A JP6128179 A JP 6128179A JP 6128179 A JP6128179 A JP 6128179A JP S55154638 A JPS55154638 A JP S55154638A
Authority
JP
Japan
Prior art keywords
error
processing
multiplex
latch
error processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6128179A
Other languages
Japanese (ja)
Other versions
JPS612217B2 (en
Inventor
Seiichiro Yamamoto
Kenichiro Oda
Toshiaki Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6128179A priority Critical patent/JPS55154638A/en
Publication of JPS55154638A publication Critical patent/JPS55154638A/en
Publication of JPS612217B2 publication Critical patent/JPS612217B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To perform error processing efficiently, by performing the error processing to all the devices if multiplex error is displayed with multiplex error latch and processing to the error processing only in other cases.
CONSTITUTION: When an error detection circuit 9 detects an error, an error address register 10 performs error processing request to program. In this case, the address of the device during processing is tentatively stored in an error latch 11, but if a new error is detected at that stage, the address is stored in the multiplex error latch. Further, if the program receives the error processing and a latch 12 does not display the multiplex error, processing is made to the latch 11, and if multiplex error is displayed with the multiplex error latch 12, error processing is made to all the devices. Thus, error processing can efficiently be made by avoiding the processing to all the devices other than multiplex error display.
COPYRIGHT: (C)1980,JPO&Japio
JP6128179A 1979-05-18 1979-05-18 Error processing system Granted JPS55154638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6128179A JPS55154638A (en) 1979-05-18 1979-05-18 Error processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6128179A JPS55154638A (en) 1979-05-18 1979-05-18 Error processing system

Publications (2)

Publication Number Publication Date
JPS55154638A true JPS55154638A (en) 1980-12-02
JPS612217B2 JPS612217B2 (en) 1986-01-23

Family

ID=13166657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6128179A Granted JPS55154638A (en) 1979-05-18 1979-05-18 Error processing system

Country Status (1)

Country Link
JP (1) JPS55154638A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0358414U (en) * 1989-10-09 1991-06-06

Also Published As

Publication number Publication date
JPS612217B2 (en) 1986-01-23

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