JPS55135949A - Soft test support device of microcontroller - Google Patents

Soft test support device of microcontroller

Info

Publication number
JPS55135949A
JPS55135949A JP4336379A JP4336379A JPS55135949A JP S55135949 A JPS55135949 A JP S55135949A JP 4336379 A JP4336379 A JP 4336379A JP 4336379 A JP4336379 A JP 4336379A JP S55135949 A JPS55135949 A JP S55135949A
Authority
JP
Japan
Prior art keywords
circuit
microcontroller
controller
information
processing step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4336379A
Other languages
Japanese (ja)
Inventor
Masahiko Sato
Koji Kotaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4336379A priority Critical patent/JPS55135949A/en
Publication of JPS55135949A publication Critical patent/JPS55135949A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: The main control circuit controls transfer of information in accordance with the instructions which is provided through the detection signal of the MATCH format circuit and the I/O bus interface circuit, and easily performs the analysis of failure of hardware of the microcontroller.
CONSTITUTION: The microcontroller interface circuit 12 sends and receives information to and from the microcontroller 1 which should perform a soft test, and receves information of the bus of this controller 1. And a register group 15 stores a processing step of the controller 1 which is provided from a large-sized computer through the I/O bus interface circuit 14, and it is detected that the processing step stored in the register group 15 by the MATCH format circuit 16 conforms to the processing step whose operation is being executed, of the controller 1. At this stage, the main control circuit 17 controls transfer of information in accordance with the instructions provided through the detection signal of the circuit 16 and the circuit 14. Thus, both the analysis of failure concerning hardware of the controller 1 and the retrieval of failure of soft logic can be carried out easily.
COPYRIGHT: (C)1980,JPO&Japio
JP4336379A 1979-04-10 1979-04-10 Soft test support device of microcontroller Pending JPS55135949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4336379A JPS55135949A (en) 1979-04-10 1979-04-10 Soft test support device of microcontroller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4336379A JPS55135949A (en) 1979-04-10 1979-04-10 Soft test support device of microcontroller

Publications (1)

Publication Number Publication Date
JPS55135949A true JPS55135949A (en) 1980-10-23

Family

ID=12661765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4336379A Pending JPS55135949A (en) 1979-04-10 1979-04-10 Soft test support device of microcontroller

Country Status (1)

Country Link
JP (1) JPS55135949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291036B1 (en) * 1999-03-03 2001-05-15 윤종용 Apparatus and method for managing system hardware using micro-controller and standard I2C bus protocol

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291036B1 (en) * 1999-03-03 2001-05-15 윤종용 Apparatus and method for managing system hardware using micro-controller and standard I2C bus protocol

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