JPS5523564A - Input/output control unit - Google Patents

Input/output control unit

Info

Publication number
JPS5523564A
JPS5523564A JP9613978A JP9613978A JPS5523564A JP S5523564 A JPS5523564 A JP S5523564A JP 9613978 A JP9613978 A JP 9613978A JP 9613978 A JP9613978 A JP 9613978A JP S5523564 A JPS5523564 A JP S5523564A
Authority
JP
Japan
Prior art keywords
signal
unit
control unit
srvi
anomaly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9613978A
Other languages
Japanese (ja)
Other versions
JPS607823B2 (en
Inventor
Toshio Matsumoto
Seiichi Yasumoto
Masakazu Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53096139A priority Critical patent/JPS607823B2/en
Publication of JPS5523564A publication Critical patent/JPS5523564A/en
Publication of JPS607823B2 publication Critical patent/JPS607823B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To cause an I/O control unit itself to self-initialize by detecting anomaly of the interface control in the I/O control unit when anomaly of tag response is detected by the processing unit after selecting the I/O control unit.
CONSTITUTION: I/O control unit 3 issues tag signal SRVI to perform data transfer request. The processing unit answers with signal SRVO. Next, unit 3 suppresses signal SRVI. When the unit 3 side does not suppress signal SRVI over a fixed time, the processing unit detects anomaly of the interface and suppresses selection signal SLO and signal SRVO. Unit 3 detects that signal SLO has been suppressed under a signal SRVI signal issue state by bus anomaly detector 7 and generates signal GR as a self-initial signal by OR circuit 9. Unit 3 can accept restart from the processing unit due to signal GR.
COPYRIGHT: (C)1980,JPO&Japio
JP53096139A 1978-08-09 1978-08-09 input/output control device Expired JPS607823B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53096139A JPS607823B2 (en) 1978-08-09 1978-08-09 input/output control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53096139A JPS607823B2 (en) 1978-08-09 1978-08-09 input/output control device

Publications (2)

Publication Number Publication Date
JPS5523564A true JPS5523564A (en) 1980-02-20
JPS607823B2 JPS607823B2 (en) 1985-02-27

Family

ID=14157049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53096139A Expired JPS607823B2 (en) 1978-08-09 1978-08-09 input/output control device

Country Status (1)

Country Link
JP (1) JPS607823B2 (en)

Also Published As

Publication number Publication date
JPS607823B2 (en) 1985-02-27

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