JPS56123052A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS56123052A
JPS56123052A JP2702880A JP2702880A JPS56123052A JP S56123052 A JPS56123052 A JP S56123052A JP 2702880 A JP2702880 A JP 2702880A JP 2702880 A JP2702880 A JP 2702880A JP S56123052 A JPS56123052 A JP S56123052A
Authority
JP
Japan
Prior art keywords
cpus
holding
cpu
time limit
timers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2702880A
Other languages
Japanese (ja)
Other versions
JPS5816491B2 (en
Inventor
Kenichi Onishi
Minoru Nagao
Makoto Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP2702880A priority Critical patent/JPS5816491B2/en
Publication of JPS56123052A publication Critical patent/JPS56123052A/en
Publication of JPS5816491B2 publication Critical patent/JPS5816491B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To use the CPU, which has a time limit in holding, as the slave CPU, by providing plural CPUs for the master CPU and inputting the interrupt signal within the time limit of the holding slave CPU to release holding. CONSTITUTION:DFFs 15 are set to make CPUs 11 into the holding state by DMA request signal DQ to CPU1 from CPUs 11 which have internal memories 12 respectively and are connected master CPU1 and main memory 2 through common bus 8, and time counting of timers 14 is started, and interrupt signal IQ to CPUs 11 is output in a set time shorter than the time limit of CPUs 11. If DMA permission signal DA comes from CPU1 within the set time of timers 14, DFFs 15 are reset to release holding of CPUs 11, and timers 14 are reset also. As a result, the CPU having a time limit in holding is used as the slave CPU.
JP2702880A 1980-03-03 1980-03-03 multiprocessor system Expired JPS5816491B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2702880A JPS5816491B2 (en) 1980-03-03 1980-03-03 multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2702880A JPS5816491B2 (en) 1980-03-03 1980-03-03 multiprocessor system

Publications (2)

Publication Number Publication Date
JPS56123052A true JPS56123052A (en) 1981-09-26
JPS5816491B2 JPS5816491B2 (en) 1983-03-31

Family

ID=12209610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2702880A Expired JPS5816491B2 (en) 1980-03-03 1980-03-03 multiprocessor system

Country Status (1)

Country Link
JP (1) JPS5816491B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0234894U (en) * 1988-08-30 1990-03-06

Also Published As

Publication number Publication date
JPS5816491B2 (en) 1983-03-31

Similar Documents

Publication Publication Date Title
JPS55134459A (en) Data processing system
DK381686A (en) PRIORITY DISTRIBUTION CIRCUIT FOR CO-OPERATING COMPUTERS
JPS57117059A (en) Multiprocessor system
JPS6481066A (en) Connection system for multi-processor
JPS56123052A (en) Multiprocessor system
JPS5622160A (en) Data processing system having additional processor
JPS57178553A (en) Multiprocessor system
JPS5671129A (en) Data processing system
JPS5549728A (en) Data transfer system
JPS5440049A (en) Information process system
JPS55116156A (en) Multiple access unit for external memory unit
JPS5696353A (en) Multiprocessor control device
JPS5672753A (en) Selective processor for occupation of common bus line
JPS5234643A (en) Multi-processing system by micro-computer
JPS5696311A (en) Bus centralized monitoring system
JPS5534752A (en) Common access unit
JPS56149659A (en) Multiprocessor system
JPS5563423A (en) Data transfer system
JPS5644925A (en) Control system of data processing system
JPS5339022A (en) Information process unit
JPS55134458A (en) Memory access system of multiprocessor system
JPS54129937A (en) Bus control system
JPS5460533A (en) Information signal control unit for common bus
JPS5687149A (en) Memory access control system
JPS5674767A (en) Multiprocessor control system