JPS56123052A - Multiprocessor system - Google Patents
Multiprocessor systemInfo
- Publication number
- JPS56123052A JPS56123052A JP2702880A JP2702880A JPS56123052A JP S56123052 A JPS56123052 A JP S56123052A JP 2702880 A JP2702880 A JP 2702880A JP 2702880 A JP2702880 A JP 2702880A JP S56123052 A JPS56123052 A JP S56123052A
- Authority
- JP
- Japan
- Prior art keywords
- cpus
- holding
- cpu
- time limit
- timers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/285—Halt processor DMA
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To use the CPU, which has a time limit in holding, as the slave CPU, by providing plural CPUs for the master CPU and inputting the interrupt signal within the time limit of the holding slave CPU to release holding. CONSTITUTION:DFFs 15 are set to make CPUs 11 into the holding state by DMA request signal DQ to CPU1 from CPUs 11 which have internal memories 12 respectively and are connected master CPU1 and main memory 2 through common bus 8, and time counting of timers 14 is started, and interrupt signal IQ to CPUs 11 is output in a set time shorter than the time limit of CPUs 11. If DMA permission signal DA comes from CPU1 within the set time of timers 14, DFFs 15 are reset to release holding of CPUs 11, and timers 14 are reset also. As a result, the CPU having a time limit in holding is used as the slave CPU.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2702880A JPS5816491B2 (en) | 1980-03-03 | 1980-03-03 | multiprocessor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2702880A JPS5816491B2 (en) | 1980-03-03 | 1980-03-03 | multiprocessor system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56123052A true JPS56123052A (en) | 1981-09-26 |
JPS5816491B2 JPS5816491B2 (en) | 1983-03-31 |
Family
ID=12209610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2702880A Expired JPS5816491B2 (en) | 1980-03-03 | 1980-03-03 | multiprocessor system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5816491B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0234894U (en) * | 1988-08-30 | 1990-03-06 |
-
1980
- 1980-03-03 JP JP2702880A patent/JPS5816491B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5816491B2 (en) | 1983-03-31 |
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