JPS5534752A - Common access unit - Google Patents

Common access unit

Info

Publication number
JPS5534752A
JPS5534752A JP10778878A JP10778878A JPS5534752A JP S5534752 A JPS5534752 A JP S5534752A JP 10778878 A JP10778878 A JP 10778878A JP 10778878 A JP10778878 A JP 10778878A JP S5534752 A JPS5534752 A JP S5534752A
Authority
JP
Japan
Prior art keywords
bus
processor
signal
indication means
comes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10778878A
Other languages
Japanese (ja)
Other versions
JPS6124741B2 (en
Inventor
Masahiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10778878A priority Critical patent/JPS5534752A/en
Publication of JPS5534752A publication Critical patent/JPS5534752A/en
Publication of JPS6124741B2 publication Critical patent/JPS6124741B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To perform the interrupt processing efficiently by using a common bus to report its own processor number and the interruptible state when each processor of plural processors becomes an interruptible state.
CONSTITUTION: Master access circuit 1 issues use request 101 to common bus 10 when processor P1 becomes an interruptible state. When use approval 102 is returned from bus 10, enable signal 103 is transferred to interrupt enable indication means 2 and address indication means 3. Indication means 2 sends a signal to bus 10 through interrupt enable signal line 104 when signal 103 comes. Indication means 3 outputs address information corresponding to processor P1 to address line 105 of use bus 10 when signal 103 comes.
COPYRIGHT: (C)1980,JPO&Japio
JP10778878A 1978-09-01 1978-09-01 Common access unit Granted JPS5534752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10778878A JPS5534752A (en) 1978-09-01 1978-09-01 Common access unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10778878A JPS5534752A (en) 1978-09-01 1978-09-01 Common access unit

Publications (2)

Publication Number Publication Date
JPS5534752A true JPS5534752A (en) 1980-03-11
JPS6124741B2 JPS6124741B2 (en) 1986-06-12

Family

ID=14468034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10778878A Granted JPS5534752A (en) 1978-09-01 1978-09-01 Common access unit

Country Status (1)

Country Link
JP (1) JPS5534752A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159565A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Interrupt input device of multicomputer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159565A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Interrupt input device of multicomputer system
JPH0114616B2 (en) * 1984-08-31 1989-03-13 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6124741B2 (en) 1986-06-12

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