JPS6124741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common access device in a system in which a plurality of processors commonly use a bus.

The so-called multi-processor system, in which a plurality of processors are combined to perform processing, allows each processor to perform processing separately, and is expected to improve processing performance.

However, the multiple processor system has various difficult problems that have delayed its development. One of the major problems is interrupt processing.

In the case of one processor, interrupt processing is
This can be relatively easily handled by a device that wishes to interrupt, as has been done in the past, by issuing an interrupt request to the processor, and when an interrupt acknowledgment is returned, it is known that the interrupt has occurred. On the other hand, in the multiple processor system, since there are multiple processors, it is difficult to know which processor to issue an interrupt to, or which processors are capable of interrupting and which ones are not.

The conventional methods have been to provide a dedicated interrupt request approval line for each processor, or to designate a processor for the device that wants to interrupt and issue the interrupt appropriately. However, the former method has many problems, such as an increase in the number of bus lines, and the latter method, such as an increase in the number of times the bus is wasted.

An object of the present invention is to perform interrupt processing efficiently in a multiple processor system, so that when each processor becomes capable of accepting interrupts, it uses a common bus to transmit address information corresponding to itself and the processor that can handle interrupts. By adopting a method of communicating this, a device that wishes to perform an interrupt can know which processors are currently capable of interrupts. The objective is to provide a common access device.

The present invention will be described in more detail below using drawings showing one embodiment.

FIG. 1 is a block diagram for explaining one embodiment of the present invention. In Figure 1, reference numeral 1
Reference numeral 2 is a master access circuit, reference numeral 2 is an interruptible display means, reference numeral 3 is an address display means, reference numeral P1 is a processor, and reference numeral 10 is a common bus line.

When the processor P1 becomes interruptible, the master access circuit 1 sends a use request 101 to the common bus 10.
issue. When the use approval 102 is returned from the common bus 10, an enable signal 103 is transmitted to the interruptible display means 2 and the address display means 3. The interruptable bulletin board means 2 sends a signal to the interruptable signal line 104 to the common bus 10 when the enable signal 103 is received.

When the address display means 3 receives the enable signal 103, it outputs address information corresponding to the processor P1 to the address line 105 of the common bus line 10.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention more clearly. In the figure, T1, T2, T3, and T4 are used to indicate the flow of time and do not specifically define time intervals. At T1, the master access circuit 1 issues a use request 101, and at T2 a use approval 102 is returned from the common bus 10. T3
When the master access circuit 1 receives the enable signal 103
At T4, the interruptable display means 2 outputs address information to the interrupt enable signal line 104, and the address display means 3 outputs address information to the address line 105.

FIG. 3 is a block diagram for explaining the interruptable notice means 2 of the present invention. In the figure, 21 is a spring drive circuit, and when an enable signal 103 comes, it sends an interrupt enable signal to the interrupt enable signal line 104 of the common bus 10. Output.

FIG. 4 is a block diagram for explaining the address display means 3 of the present invention. In the figure, 41 is a processor address setter, and 42 is a spring drive circuit. The processor address setter 41 is an array of switches that determines processor numbers. In the example shown, there are four switches, so up to 2 ⁴ =16 processors can be identified. When the bus drive circuit 42 receives the enable signal 103, the processor address setter 41 transfers the signal to the address line 105 of the common bus 10.
Outputs the address information specified in .

As can be seen from the detailed explanation of the operation of the present invention using the above example, in the present invention, when each processor of a plurality of processors becomes interrupt-enabled, a common bus is used to input the processor number of the processor that has become interrupt-enabled. By communicating this information, a device that wants to enable interrupts can know when and which processor to interrupt, and a master access circuit for using a common bus, address display means for communicating the address of the processor, The present invention provides an extremely simple and effective access device consisting of an interruptible display means for communicating an interruptible status.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. FIG. 2 is a timing chart for explaining the present invention. FIG. 3 is a block diagram of an interruptible presentation means for explaining the present invention. FIG. 4 is a block diagram of address presentation means for explaining the present invention. In the figure, 1...
... Master access circuit, 2 ... Interruptible presentation means, 3 ... Address presentation means, 10 ... Common bus line, P1 ... Processor, 101 ... Usage request,
102...Use approval, 103...Enable signal, 104...Interruptible signal line, 105...Address line, 21, 42...Bus drive circuit, 4
1...Processor address setting device.

Claims (1)

[Claims] 1. In a system in which a plurality of processors are connected by a common bus, a master access circuit issues a use request to the bus for each processor to use the common bus, and upon receiving approval from the bus, outputs an enable signal; means for indicating on the bus that the processor is interruptible when the master access circuit issues an enable signal; and means for indicating on the common bus a processor address corresponding to the processor when the enable signal is issued; 1. A common access device comprising: address display means.