JPS54102934A - Communication control system between plural processors and common input/output devices - Google Patents

Communication control system between plural processors and common input/output devices

Info

Publication number
JPS54102934A
JPS54102934A JP950178A JP950178A JPS54102934A JP S54102934 A JPS54102934 A JP S54102934A JP 950178 A JP950178 A JP 950178A JP 950178 A JP950178 A JP 950178A JP S54102934 A JPS54102934 A JP S54102934A
Authority
JP
Japan
Prior art keywords
cpu
communication
bit
turned
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP950178A
Other languages
Japanese (ja)
Inventor
Yoichi Suzuki
Setsuo Kugimiya
Akio Hanada
Teruyoshi Mita
Hiroshi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP950178A priority Critical patent/JPS54102934A/en
Publication of JPS54102934A publication Critical patent/JPS54102934A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To secure the comminucation for more than a fixed time between one unit of CPU and IO by providing the means to select the remote CPU and to memorize the start request to the IO in the communication control system in which the input/output device IO connected with plural CPU's is shared.
CONSTITUTION: The IO turns on one bit in selection register 4 via the program and then accepts the start request from the corresponding CPU. In case the start requests are given from other CPU's, the busy signal is sent back from FF1 and corresponding one bit in start request memory register 3 is turned on since the selection bit corresponding to the CPU is off. AFter end of the communication, the CPU with which the bit of register 3 is turned on is selected. Thus, the communication end information is sent to the CPU, and at the same time one bit in register 3 is turned off. The selection bit is informed to the program after communication and turned off simultaneously. Thus, the priority-selected CPU and IO are displayed to be in use even though the communication is carried out between them, ensuring the communication of more then a fixed time.
COPYRIGHT: (C)1979,JPO&Japio
JP950178A 1978-01-31 1978-01-31 Communication control system between plural processors and common input/output devices Pending JPS54102934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP950178A JPS54102934A (en) 1978-01-31 1978-01-31 Communication control system between plural processors and common input/output devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP950178A JPS54102934A (en) 1978-01-31 1978-01-31 Communication control system between plural processors and common input/output devices

Publications (1)

Publication Number Publication Date
JPS54102934A true JPS54102934A (en) 1979-08-13

Family

ID=11721977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP950178A Pending JPS54102934A (en) 1978-01-31 1978-01-31 Communication control system between plural processors and common input/output devices

Country Status (1)

Country Link
JP (1) JPS54102934A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2521777A1 (en) * 1982-02-18 1983-08-19 Varian Associates METHOD AND APPARATUS FOR BEAM SCANNING FOR ION IMPLANTATION

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2521777A1 (en) * 1982-02-18 1983-08-19 Varian Associates METHOD AND APPARATUS FOR BEAM SCANNING FOR ION IMPLANTATION

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