JPS56168254A - Advance control system for input/output control unit - Google Patents

Advance control system for input/output control unit

Info

Publication number
JPS56168254A
JPS56168254A JP7207580A JP7207580A JPS56168254A JP S56168254 A JPS56168254 A JP S56168254A JP 7207580 A JP7207580 A JP 7207580A JP 7207580 A JP7207580 A JP 7207580A JP S56168254 A JPS56168254 A JP S56168254A
Authority
JP
Japan
Prior art keywords
input
bus
output
memory
accomplished
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7207580A
Other languages
Japanese (ja)
Inventor
Kazuo Sumiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7207580A priority Critical patent/JPS56168254A/en
Publication of JPS56168254A publication Critical patent/JPS56168254A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To realize advance control by making it possible for an input/output control device to receive the start of input/output operations to be executed next in the space time produced at every unit transfer of data during data transfer, in a data processing system. CONSTITUTION:Starting of an input/output control device IOC is accomplished when address information is sent from a CPU (not shown) to an address bus AB, the byte count information in a data bus DB is inputted to a random access memory CRAM for control in the desingated control device IOC, and thereafter, memory addresses, commands, etc. are sent via the bus and stored in respective registers in the memory CRAM, whereby the input and output operations are accomplished. If there is the start from the CPU during the input and output operation, a device control part D-CTL immediately generates a start acceptance signal STA when there are no use conditions of the memory CRAM, but if there are the conditions for using the memory CRAM, various kinds of control information from the bus are stored in the waiting registers BCR', MAR', etc. in the memory CRAM after its use, whereby the preparation for the next transfer operation is accomplished.
JP7207580A 1980-05-29 1980-05-29 Advance control system for input/output control unit Pending JPS56168254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7207580A JPS56168254A (en) 1980-05-29 1980-05-29 Advance control system for input/output control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7207580A JPS56168254A (en) 1980-05-29 1980-05-29 Advance control system for input/output control unit

Publications (1)

Publication Number Publication Date
JPS56168254A true JPS56168254A (en) 1981-12-24

Family

ID=13478918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7207580A Pending JPS56168254A (en) 1980-05-29 1980-05-29 Advance control system for input/output control unit

Country Status (1)

Country Link
JP (1) JPS56168254A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124763A (en) * 1983-12-12 1985-07-03 Hitachi Ltd Input/output controller
JPS60237556A (en) * 1984-05-09 1985-11-26 Fuji Facom Corp Data transfer control system
JPH01159754A (en) * 1987-12-16 1989-06-22 Fujitsu Ltd Data processing system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124763A (en) * 1983-12-12 1985-07-03 Hitachi Ltd Input/output controller
JPH0118460B2 (en) * 1983-12-12 1989-04-05 Hitachi Ltd
JPS60237556A (en) * 1984-05-09 1985-11-26 Fuji Facom Corp Data transfer control system
JPH01159754A (en) * 1987-12-16 1989-06-22 Fujitsu Ltd Data processing system

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