JPS5614329A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5614329A
JPS5614329A JP9021079A JP9021079A JPS5614329A JP S5614329 A JPS5614329 A JP S5614329A JP 9021079 A JP9021079 A JP 9021079A JP 9021079 A JP9021079 A JP 9021079A JP S5614329 A JPS5614329 A JP S5614329A
Authority
JP
Japan
Prior art keywords
signal
cycle
bus
information transfer
read cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9021079A
Other languages
Japanese (ja)
Other versions
JPS6248259B2 (en
Inventor
Yutaka Onodera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9021079A priority Critical patent/JPS5614329A/en
Publication of JPS5614329A publication Critical patent/JPS5614329A/en
Publication of JPS6248259B2 publication Critical patent/JPS6248259B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To utilize effectively the bus cycle to reduce the number of signal lines, by using the information transfer read cycle in stead of the status signal read cycle and the information transfer cycle in respect of asynchronous conversation type bus transfer between units connected to the common bus.
CONSTITUTION: When processor CPU and the I/O control unit are the master and the slave respectively, the transferring indication signal is output from the CPU to common bus 3. This signal is supplied to respective response circuits 1 of plural units connected to common bus 3. When this transferring indication signal is emitted by decoding circuit 2, this signal generates a strobe signal obtained after fixed-time delay. At the generation time of the strobe signal, the information transfer status signal read cycle consisting of a response signal and a status signal is generated. As a result, the one-cycle bus of the information transfer status signal read cycle can be used in stead of the status signal read cycle and the information transfer cycle, so that the bus cycle can be utilized effectively to reduce the number of signal lines.
COPYRIGHT: (C)1981,JPO&Japio
JP9021079A 1979-07-16 1979-07-16 Data processing system Granted JPS5614329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9021079A JPS5614329A (en) 1979-07-16 1979-07-16 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9021079A JPS5614329A (en) 1979-07-16 1979-07-16 Data processing system

Publications (2)

Publication Number Publication Date
JPS5614329A true JPS5614329A (en) 1981-02-12
JPS6248259B2 JPS6248259B2 (en) 1987-10-13

Family

ID=13992114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9021079A Granted JPS5614329A (en) 1979-07-16 1979-07-16 Data processing system

Country Status (1)

Country Link
JP (1) JPS5614329A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267850A (en) * 1985-05-17 1986-11-27 Panafacom Ltd Shared bus control system
WO2003071437A1 (en) * 2002-02-21 2003-08-28 Sony Corporation External connection device, host device, and data communication system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5065144A (en) * 1973-10-11 1975-06-02
JPS5123046A (en) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS51113546A (en) * 1975-03-31 1976-10-06 Hitachi Ltd Information transmitting system
JPS5211837A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Input-output interface starting method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5065144A (en) * 1973-10-11 1975-06-02
JPS5123046A (en) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS51113546A (en) * 1975-03-31 1976-10-06 Hitachi Ltd Information transmitting system
JPS5211837A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Input-output interface starting method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267850A (en) * 1985-05-17 1986-11-27 Panafacom Ltd Shared bus control system
WO2003071437A1 (en) * 2002-02-21 2003-08-28 Sony Corporation External connection device, host device, and data communication system
US7051128B2 (en) 2002-02-21 2006-05-23 Sony Corporation System and method for data bus communication system between external card connection device and host device
CN1297915C (en) * 2002-02-21 2007-01-31 索尼公司 External connection device, host device and data communication system
US7318113B2 (en) 2002-02-21 2008-01-08 Sony Corporation System and method communication system for reading or writing data to register between external card connection device and host device
KR100987205B1 (en) 2002-02-21 2010-10-12 소니 주식회사 External connection device, host device, and data communication system

Also Published As

Publication number Publication date
JPS6248259B2 (en) 1987-10-13

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