JPS55150048A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55150048A
JPS55150048A JP5886879A JP5886879A JPS55150048A JP S55150048 A JPS55150048 A JP S55150048A JP 5886879 A JP5886879 A JP 5886879A JP 5886879 A JP5886879 A JP 5886879A JP S55150048 A JPS55150048 A JP S55150048A
Authority
JP
Japan
Prior art keywords
order
storage request
retrial
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5886879A
Other languages
Japanese (ja)
Inventor
Toshiyuki Furui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5886879A priority Critical patent/JPS55150048A/en
Publication of JPS55150048A publication Critical patent/JPS55150048A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the time region where the retrial of the order is possible with a reduced number of hardwares, by providing the function which retains the information storage request to the main memory in the high-speed buffer memorization for the order to give alteration to the main memory.
CONSTITUTION: The order process control circuit of process part 1 detects the impossibility of the order retrial by giving alteration to the information of main memory 2 with the storage request occurring under execution of the order. Then the signals of the storage request and storage retaining are sent to high-speed buffer memory control circuit 20, and circuit 20 stores the signal sent in the same way as the storage request in case the address block exists on the high-speed buffer memory into buffer memory circuit 3 and dose not give the storage request to memory 2. And then the storage request which makes the order retrial impossible is processed within circuit 20, and the time region where the order retrial is impossible is changed to the state under which the order retrial is possible.
COPYRIGHT: (C)1980,JPO&Japio
JP5886879A 1979-05-14 1979-05-14 Information processor Pending JPS55150048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5886879A JPS55150048A (en) 1979-05-14 1979-05-14 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5886879A JPS55150048A (en) 1979-05-14 1979-05-14 Information processor

Publications (1)

Publication Number Publication Date
JPS55150048A true JPS55150048A (en) 1980-11-21

Family

ID=13096706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5886879A Pending JPS55150048A (en) 1979-05-14 1979-05-14 Information processor

Country Status (1)

Country Link
JP (1) JPS55150048A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5355917A (en) * 1976-10-29 1978-05-20 Nec Corp Buffer memory unit
JPS5372545A (en) * 1976-12-10 1978-06-28 Nec Corp Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5355917A (en) * 1976-10-29 1978-05-20 Nec Corp Buffer memory unit
JPS5372545A (en) * 1976-12-10 1978-06-28 Nec Corp Information processor

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