JPS5660955A - Interruption priority determination system - Google Patents

Interruption priority determination system

Info

Publication number
JPS5660955A
JPS5660955A JP13591579A JP13591579A JPS5660955A JP S5660955 A JPS5660955 A JP S5660955A JP 13591579 A JP13591579 A JP 13591579A JP 13591579 A JP13591579 A JP 13591579A JP S5660955 A JPS5660955 A JP S5660955A
Authority
JP
Japan
Prior art keywords
interruption
time width
control signal
control
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13591579A
Other languages
Japanese (ja)
Inventor
Takayuki Fujita
Minoru Machida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP13591579A priority Critical patent/JPS5660955A/en
Publication of JPS5660955A publication Critical patent/JPS5660955A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to determine interruption priority by a simple hardware method by using a group of pulse signals differing in time width and generated exclusively one another as the control signal for priority determination.
CONSTITUTION: Interruption factors IF1WIF4 generated completely at random are brought under the gate control of gate group G1 by control signals CSAWCSD differing in time width. An interruption factor under the gate control by a control signal of longer time width is accepted by CPU more possibly than that under the gate control by a control signal of shorter time width. On the other hand, CPU, when accepting the interruption, outputs information as a vector address to address bus lines A0WAn and it is transferred to the memory unit. Thus, the allotting determination of the interruption priority can be performed by an extremely simple hardware method.
COPYRIGHT: (C)1981,JPO&Japio
JP13591579A 1979-10-23 1979-10-23 Interruption priority determination system Pending JPS5660955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13591579A JPS5660955A (en) 1979-10-23 1979-10-23 Interruption priority determination system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13591579A JPS5660955A (en) 1979-10-23 1979-10-23 Interruption priority determination system

Publications (1)

Publication Number Publication Date
JPS5660955A true JPS5660955A (en) 1981-05-26

Family

ID=15162807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13591579A Pending JPS5660955A (en) 1979-10-23 1979-10-23 Interruption priority determination system

Country Status (1)

Country Link
JP (1) JPS5660955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644489A2 (en) * 1993-09-20 1995-03-22 International Business Machines Corporation Method and apparatus for signalling interrupt information in a data processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644489A2 (en) * 1993-09-20 1995-03-22 International Business Machines Corporation Method and apparatus for signalling interrupt information in a data processing system
EP0644489A3 (en) * 1993-09-20 1995-11-22 Ibm Method and apparatus for signalling interrupt information in a data processing system.

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