JPS56149659A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS56149659A
JPS56149659A JP5249480A JP5249480A JPS56149659A JP S56149659 A JPS56149659 A JP S56149659A JP 5249480 A JP5249480 A JP 5249480A JP 5249480 A JP5249480 A JP 5249480A JP S56149659 A JPS56149659 A JP S56149659A
Authority
JP
Japan
Prior art keywords
access
processor
memory
bit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5249480A
Other languages
Japanese (ja)
Other versions
JPS6119059B2 (en
Inventor
Eiichi Kagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5249480A priority Critical patent/JPS56149659A/en
Publication of JPS56149659A publication Critical patent/JPS56149659A/en
Publication of JPS6119059B2 publication Critical patent/JPS6119059B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To avoid breakdown of data and thus increase the process efficiency of a multi-processor system, by inhibiting an access given to the same memory by the 2nd processor only when the 1st processor renews a shared memory by every bit. CONSTITUTION:For a system in which the processors 1 and 2 share the memory 6, the processor 1 delivers the bus request signal REQ1 to give an access with every word and the bit write access signal BAC1 to give an access with every bit to the bus controller 3. As a result, the processor 1 is connected to the memory 6 via the bus change-over device 5, and the processor 1 gives an access to the specified address C of the memory 6. With the end of this access, the signal REQ1 is reset until the signal BAC1 is reset. Even REQ2 and BAC of the processor 2 are set (with access request to memory 6) the bit access controller 4 gives no permission of access to the processor 2.
JP5249480A 1980-04-18 1980-04-18 Multiprocessor system Granted JPS56149659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5249480A JPS56149659A (en) 1980-04-18 1980-04-18 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5249480A JPS56149659A (en) 1980-04-18 1980-04-18 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPS56149659A true JPS56149659A (en) 1981-11-19
JPS6119059B2 JPS6119059B2 (en) 1986-05-15

Family

ID=12916261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5249480A Granted JPS56149659A (en) 1980-04-18 1980-04-18 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS56149659A (en)

Also Published As

Publication number Publication date
JPS6119059B2 (en) 1986-05-15

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