JPS57168348A - Pipeline computer - Google Patents
Pipeline computerInfo
- Publication number
- JPS57168348A JPS57168348A JP5349481A JP5349481A JPS57168348A JP S57168348 A JPS57168348 A JP S57168348A JP 5349481 A JP5349481 A JP 5349481A JP 5349481 A JP5349481 A JP 5349481A JP S57168348 A JPS57168348 A JP S57168348A
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- sink signal
- processing
- write operation
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
Abstract
PURPOSE:To perform the write operation and the execution processing in parallel, by returning a slave sink signal immediately after a memory device receives a master sink signal in the pipeline computer having the operand prefetching function. CONSTITUTION:When a memory device 1 receives a memory bus master sink signal from a CPU 3, and device 1 returns a memory bus slave sink signal immediately simultaneously with starting the write operation. When receiving this memory bus slave sink signal, the CPU 3 restarts the instruction processing. In the CPU 3, a program counter is counted up to transfer the control to the processing for the next instruction after the processing for a store instruction is completed. Thus, the CPU 3 executes successively processings for instructions following the store instruction in the course of the write operation to the memory device 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5349481A JPS57168348A (en) | 1981-04-09 | 1981-04-09 | Pipeline computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5349481A JPS57168348A (en) | 1981-04-09 | 1981-04-09 | Pipeline computer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57168348A true JPS57168348A (en) | 1982-10-16 |
JPS612972B2 JPS612972B2 (en) | 1986-01-29 |
Family
ID=12944379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5349481A Granted JPS57168348A (en) | 1981-04-09 | 1981-04-09 | Pipeline computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57168348A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63182185U (en) * | 1987-05-15 | 1988-11-24 |
-
1981
- 1981-04-09 JP JP5349481A patent/JPS57168348A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS612972B2 (en) | 1986-01-29 |
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