JPS5812188A - Information processor - Google Patents

Abstract

PURPOSE:To perform the reading or write of a data through a main memory, by receiving the write address of the main memory of another processor and conductive a coincidence of data between a cash memory and the main memory. CONSTITUTION:To cash control parts 1 and 1' having the same constitution and stored in different processors contain the cash memories 10 and 10'. A memory access control part 2 decides the priority for the request soruces, the designation of the main memories 3 and 3' and the using condition of the main memory to an access request given to the memories 3 and 3' from each cash control part. Then a selecting circuit 20 selects an access request given from a request source. For a processor at the side of the control paat 1, an address line 11 is selected to give an access to the main memory. At the same time, the address is applied to an address line 23 for process of the cash coincidence by the selection of the address request source and via a switch circuit that selects the signal lines 22 and 22'.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a device having a cashier memory, receiving a main memory write address of another processing device, and performing data matching between the cashier memory and the main memory. The present invention relates to an information processing apparatus that continuously outputs or writes data from a main memory regardless of whether or not the data is currently present in a memory.

Even if there is a system K) in which data consistency between the main memory 49 and the cache memory is guaranteed by hardware, there is a time lag in the time when rewriting data on the main memory is reflected in the cache memory. When accessing data where this time difference is a problem, the software is tested and set (T8
) Instruction 0IlikI! # A method is used to read and write directly from the main memory using special instructions.

However, if this data already exists in the cache memory, the conventional device remembers its location and displays the main message.
It is complicated and requires a lot of hardware to read out the data and replace it with new data or invalidate the data in the cache control section. Furthermore, having one person perform this control on the i-controller memory, which has a severe circuit delay time, lengthened the equipment's machine time and resulted in a drop in performance.

The purpose of the present invention is to guarantee data consistency between the main memory and cache memory when directly reading from and writing to the main memory, thereby reducing the amount of hardware in the cache control unit and the complexity of control.
Another object of the present invention is to provide an i-information processing device which can invalidate data corresponding to an address from a cache without deteriorating the performance of the device.

In order to achieve the above object, an information processing device according to the present invention has a cache memory, receives a main memory write address of another processing device, and performs cache matching and data matching between the main memories. , regardless of whether or not the required data is on the cache memory) 1k< In the information unit Im device that functions to extract or write data from the main memory, matching processing is required for the own processing device. It has a matching processing request generating circuit that generates a signal corresponding to whether it is reading or writing, and when the reading or writing requires matching processing for the own processing device, the address of the subsequent reading or writing. is used as a match guarantee address, and is sent to the own processing device to ensure data match between the main memory and the cache memory.

In other words, in the present invention, when a special operation that ignores the cashier, such as a test F AND set command, is instructed, the cashier control unit unconditionally clears the data at that address in the cache memory, regardless of whether there is data at that address, and performs a special main memory access. , and activates main memory access via the memory access control unit. Then, the memory access control unit detects that the main memory is a special main memory access waiting for startup, and sends the address to its own 0PUK), and instructs the cache memory to ensure consistency between the main memory and the cache memory. The control unit is designed to process the data exactly the same as that from other processing devices.

According to the above configuration, the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings. .

FIG. 1 shows an embodiment of the present invention, in which the main memory and cache knee are accessed to the main memory. FIG. 2 is a schematic diagram showing the relationship between guarantee requests (hereinafter simply referred to as cache matching processing), focusing on the flow of addresses;

1.1' are cache control units of the same configuration housed in different processing devices, each including a cache memory 10.10'. Reference numeral 2 is a memory access control unit which determines the priority of the request source and the main memory 3.3' in response to an access request from the cache control unit to the main memory 3.3'. '3'
The selection circuit 20 selects an access request from one request source by determining the specification and the usage status of the main memory, for example,
If the device has a cache control unit 1, the address line 11 is selected and the main memory is accessed, and at the same time, the address is transferred via the switching circuit 21 to the middle address 1s for match processing! Send SK.

When the request source connected to its own memory access control unit is selected, the switching circuit 1 transfers the contents of the signal line 22 to another source 4.
qConnect to the access control unit! This circuit is for selecting the content of the signal line 22' and sending it to the signal line 33 when the requested source is selected.

3' is also a memory access control section and memory access control II.
Perform the same operation as 2. Note that a part of the circuit of the memory access controller 2' is omitted. 34
Reference numeral 41 denotes a matching processing request generation circuit that determines a processing device to issue a matching processing request. FIG. 2 shows a detailed diagram of this coincidence processing request generation circuit. Each coincidence processing request generation circuit 30, 31 is 40 corresponding to a device accommodating the cache control section 1 and a device accommodating the cache control section 1', respectively. When the processing device on the cache control unit i side starts accessing the main memory, the signal line 40 is connected to It becomes 1. Furthermore, in the case of a main memory read request that requires matching processing for the current request @*flK, the signal line 42 becomes 1, and in the case of a write, the signal line 44 becomes 1. Note that the signal lines 40 and 41 are connected to the memory access control section of the extension and become O when nine devices are selected or there is no device to be selected. The signal line 43 becomes l in the case of a write request to the main memory that does not require matching processing. The signal line so;sx is connected to the same device KI as the requesting device indicated by the signal line 40.
I will be sewn.

Signal @1 from the match processing request generation circuit as described above
K instructs matching processing of the cache memory of the own processing device.

For example, suppose that a main memory read request requiring matching processing occurs in the processing device @ including the cache control unit l, the signal line 40. Since the signal line 42Fi becomes ``1'''', the signal line go becomes 11''.As a result, the cache control unit 1 writes the address on the signal line 23 in the same way as when receiving the main memory write address from the other #! & san device. It is checked whether the data corresponding to the above is present on the cashier JFQ, and if the data is present, an operation is performed to invalidate the data.

As explained in detail above, the present invention has a matching processing request generation circuit, and is configured to use the cashier matching processing request 07 according to instructions from this circuit. As in the case of , if the main method that ignores the cache memory (re-accesses) is efficiently returned to the main method of the own processing device, it is possible to guarantee consistency between the cache memories.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram illustrating an embodiment of an information processing apparatus according to the present invention, focusing on the flow of addresses, and FIG. 2 is a circuit diagram illustrating an embodiment of the matching processing request generation circuit of FIG. be. 1.1'--Memory access control section 3.3'--Main memory 10.10'--Cache memory 2040', 21.21'--Selection Circuit 30.31
- Match processing request generating circuit patent applicant NEC Corporation Representative Patent attorney Hisashi I) Ro

Claims (1)

[Claims] A device that has a cashier memory, receives the main memory write address of another processing device, and performs data matching between the cashier memory and the main memory, and is concerned with the presence or absence of required data on the cache memory. In an information processing device that functions to read or write data from/to the main memory, a coincidence that generates a signal corresponding to whether or not the reading or writing requires matching/processing for the own processing device. It has a processing S* request generation circuit, and when reading or writing requires matching processing to the own processing device, the read or write address is sent to the own processing device as a match guarantee address. An information processing device characterized in that it is configured to guarantee data consistency between a main memory and an intermediate memory.