GB1578205A - Communication between units in a multiprocessor system - Google Patents

Description

(54) COMMUNICATION BETWEEN UNiTS IN A MULTIPROCESSOR SYSTEM (71) We, HONEYWELL INFORMATION SYSTEMS INC., a Corporation organised and existing under the laws of the State of Delaware, United States of America of 200 Smith Street, Waltham, Massachusetts 02154, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed to be particularly described in and by the following statement:- This invention relates to a multiprocessor data processing system, and particularly to means by which one processor communicates with another processor of the system to cause the latter processor to initiate an action required by the given processor.

In certain current large computer systems, when there is a need for an input/output (I/O) operation, a request for such an operation, sometimes designated as a "connect" instruction is generated by a central processing unit (CPU) under the control of the operating system of the computer system.

The operating system through the CPU in response to the receipt of a connect instruction produces I/O control information identifying a port on a system controller to which the peripheral device to be used in the I/O operation is connected. The system controller generates an interrupt signal and uses the port number to route the interrupt signal to the processor controlling the peripheral device. The processor to which the interrupt signal is transmitted in response to its receipt obtains the necessary information to be used in the desired I/O operation from its mailbox, a predetermined location in working store of the overall system.

In an existing form of data processing system there are eight ports on a system controller to which an interrupt signal can be sent in response to the receipt of a connect command; thus a three bit field in a data word can be and is used to identify the port of the SCU to which the interrupt is to be sent, and the port number thus identifies the processor to which an interrupt signal is to be directed.

When an improved data processing system is being developed one of the requirements frequently imposed on the design is that it be compatible with earlier systems of that manufacture, so that programs and, in particular, application programs, which will run on earlier systems, will operate on the improved system without significant reprograming. Thus an improved data processing system may have the capability of having up to a maximum of eight processors (I/O processors and CPU processors) connected into the system, so that a given CPU can communicate with up to eight such processors (since a processor can communicate with itself) in response to the receipt of a connect instruction in the same format as in the earlier systems. The improved data processing system, in its maximum configuration, is comprised of two system interface units (SIU)s each of which has eight ports to which an I/O processor or a CPU can be connected. Thus, a three bit field in a data word which was capable in earlier systems of uniquely designating the port and thus the processor to which the connect communication to be directed is no longer sufficient to provide the necessary information required in the new data processing system.

The number of processors to which such a communication can be sent is eight, which in principle can be uniquely described by a three bit field; however, since these eight processors can be connected to sixteen different ports in the SIUs and different types of processors, the I/O and the CPUs in the new system require different types of communication signals. Thus the three bit field of the earlier system is no longer adequate to satisfy the informational requirements to implement the connect in struction in the new system.

The general object of the present invention is therefore to provide a system by which one processor in a multiprocessor system can communicate with another without specifying directly the processor to be communicated with.

According to the present invention there is provided a data processing system comprising: an SIU (system interface unit) having a plurality of ports; a plurality of processing units, including at least one CPU, coupled to respective ports; and at least one main memory coupled to a respective main memory controller included in the SIU, wherein the or each CPU includes means responsive to a connect command including a destination code to - combine the contents of a predetermined register (reserve memory segment base address) with the destination code to form a memory address and cause the contents of that address to be read, those contents forming WRRR (write remote register) data including a code identify ing an SIU port, - generate a WRRR instruction, and - transmit the WRRR instruction and WRRR data to the SIU.

Tn the system to be described in detail, the connect command consists of two words, a connect instruction word followed by a data word.

A data processing system embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of the improved multiprocessor data processing system.

Figure 2 is a flow chart of the connect microprogram.

Figure 3 is a block diagram of the components of a CPU which in response to control signals derived from the microprogram initiate communication with another processor of the system.

Figure 4 is the format of a part of the reserve memory portion of a main memory of the system.

Figure 5 is the format of instruction words and data words used in the data processing system of Figure 1.

Before describing the system in detail, it will be briefly summarized. In the course of carrying out a sequence of operations, a processor (e.g. CPU 16a. Fig. 1) may receive a connect command. This command consists of a connect instruction word (Fig.

5A) followed by a data word (Fig. 5B) containing a 3 bit code (bits 33 to 35) indicating which of a variety of other units the CPU is to communicate with. The connect instruction causes the CPU to start a connect microprogram (Fig. 2). On the first microinstruction, the second word (data word) of the connect command is read, and the 3-bit destination code is stored in a temporary register (TRO, Fig. 3). Also, the base address of a Reserve Memory Segment (Fig. 4) in a main memory MMo 22a is read out of its normal location, location 7 of a scratch-pad memory SPM and put into a temporary register TBASE U. In microinstruction 2, a fixed offset of 4 is added to this base address and the word in that location of the reserve memory segment is read out in microinstruction 3. This word gives an offset within the reserve memory segment to the start of a table of connect data words. On the fourth microinstruction, this offset is added to the destination code and the sum stored in a temporary register TEA 0. Also on this and the next microinstruction, the word in the next location (location 5) in the reserve memory segment is read out and stored in a temporary register TR1.

This word is the write remote register communication command, WRRR Commn.

Command, Fig. 5C. Also on microinstruction 5 the contents of TEA 0 and TBASE 0 are added to locate the entry, in the table of connect data words, of a pair of words (Figs. SD and SE) associated with the particular destination code in the connect command data word (Fig. SB). The first of these connect data words is read out into a temporary register TR2, and consists of WRRR data for connect to a particular CPU or IOP (Fig. 1). This is tested to see whether it relates to a non-existent processor. The second connect data word is next read, this containing a code bit (PRO) identifying whether the communication is to be with an IOP (input/output processor) or a CPU (central processing unit), a code bit (SIU) identifying which of two SIU's (system interface units) 12a and 12b (Fig. 1) is to be communicated with, and a 4-bit field (SIU-P) identifying which port on the selected SIU is to be communicated with.

The WRRR/COMM command is sent to a main memory controller which enters it into its command stack like any other memory command. The two WRRR data words are transmitted to the designated processor.

Considering the system now in detail, Figure 1 is a block diagram of a maximum configuration with respect to processors of the improved data processing system 10.

Data processing system 10 has two WIU's 12a and 12b. Each SIU 12 has 15 ports identified by letters A to K plus four additional memory ports, local memory port 0 (LM,), local memory port 1 (LM1), and two main memory ports in which the main memory control function or controllers (MMCo) and (MMC1) are located. On certain pairs of ports such as G and H and ports E and F, a pair of locked I/O processors 14a, 14b, 14c, 14d can be attached.

Up to four central processing units 16a, 16b, 16c and 16d, two to each SIU, can be attached to any two of ports A, to H of each SIU. Local memories (LMo) 18a, to 18d can be connected to the local memory ports 20a to 20d of the SIU's and main memories 22a 22d can be connected to the main memory controllers MMCo and MMC1 of the SIU's 12a and 12b. Each of the main memory controllers MMC, 24a, 24c and MMCz 24b, 24d of the SIU's 12a, 12b has two ports and each of the main memories 20a and 20b also has two ports which are cross-connected to permit communication to occur between devices and memories attached to the respective SIU's 12.

Each of the main memory controllers MMCo 24a, 24c MMC1 24b, 24d of SIUs 12a, 12b has in addition to writing data into a main memory MMa 22a, 22c, or MM 22b, 22d and to reading data out of an MMo or MM1, certain communication control functions as well.

Communications between SIU's can be from a main memory controller such as MMCo 24a of SIU 12a to the main memory MMn 22C of SIU 12b. MM1 22c communicates or transmits the message to its main memory controller MMCo 24c of SIU 12b.

MMCn 24c in turn directs the communication to the designated port of SIU 12b to which is attached a processor such as IOP/P 14c or CPU 16c, for example, of SIU 12b the processor to which the communication is directed.

A CPU such as 16a in the course of performing an application program, may reach a point where an I/O operation is required either to bring in from a peripheral device data stored on the peripheral device or to read out from memory information to be transferred to a peripheral device. When the need for an I/O operation occurs, or more broadly, whenever one processor needs to communicate with another processor (including itself), the operating system of data processing system 10 will cause an instruction to be transmitted to a CPU such as 16a for example. The content of the operational field of the instruction word is such as to indicate or designate that a specific type of communication is to be performed or executed. The operating system will also provide to CPU 16a a data word a certain designated field of which will identify the processor to which the communication is to be sent. The details of the apparatus and method to do this will be more fully described later.

The field identifying the procesor is a three bit field located in the lowest order positions of the operand or data word. Fig.

5B illustrates the format of such a data word, with the field identifying the processor occupying bit positions 33-35. It can be seen, however, from Fig. 1 that it is possible to connect up to four processors to each of two SIU's 12, 12b; these processors can be connected to various ports so that the necessary information needed to uniquely identify CPU 16b or IOP 14d for example to which the communication is to be sent cannot be adequately specified by a three bit field.

Thus, additional information is required.

The additional information required is stored in a reserve memory portion of main memory such as MMa 22a of SIU 12a. The reserve memory portion illustrated in Fig.

4 of a main memory is a contiguous block of memory, whose position in main memory 22a and the data words stored therein is established at the time the data processing system 10 is initialized prior to beginning processing of application programs.

To perform the connect function, the processor has to generate the addresses in the reserve memory to fetch the necessary information so that SIU 12a can steer the communication to the correct processor on the correct SIU 12 as well as to provide that processor with the correct signals to cause it to initiate the desired function. In addition it is necessary for CPU 16a to restransmit or issue to the main memory controller MMCo 24a of SIU 12a this information.

Main memory controller MMCi 24a of SIU 12a then provides the necessary signals in the form of data words to be transmitted by SIU 12a to the addressed processor. Main memory controller 24a will recognize the communication command and the data words transmitted to its as requesting special handling. As a result, main memory controller 24a causes the necessary communication signals and information to be transmitted to the designated IOP or CPU either directly, if the designated processor is connected to the same SIU to which the main memory controller receiving the connect command is connected, or through a corresponding main memory 22c and main memory controller 24c of SIU 12b if the processor to be communicated with is attached to a port of SIU 12b. As a result of the information and signals transmitted to the designated processor, that processor knows that it is being requested to do something, and is provided with the necessary information required by the designated processor to perform the desired function whether it is an I/O function, such as is typically provided by an IOP, or some other type of function which may be performed by a CPU.

Fig. 2 is a flow chart of the connect microprogram identifying each of the microinstructions of the microprogram that is executed by a CPU's execution unit in executing the connect microprogram. Fig.

3 is a block diagram of the hardware elements of a CPU 16 which are utilized in the performance of the connect microprogram. The connect instruction is received from an instruction buffer, not shown over the instruction buffer bus Z1B 26 from main memory controller such as MMCo 24a and is transmitted through ZIB switch 28 to RBIR 30 for storage therein. Fig. 5A is the format for an instruction word with the ten bit field, bit locations 18-27, being the operation code. The operation code of an instruction word is the address in the control unit control store (CCS) 32 of a control unit control word.

The control unit control store word stored in CCS 32 has an address field which is the address of the starting location for the microprogram specified by the operation code of the instruction stored in the instruction register RBIR 30 or the address of the initial microinstruction of the microprogram.

When the op code, from an instruction, is applied to the CCS 32 from RBIR 30, the control unit control word stored at the address corresponding to the op code is accessed and the address field will be applied to the execution control store (ECS) 34 through switch CCS-ADR 36. The receipt of the address of a microinstruction by ECS 34 causes the microinstruction stored at that address to be transferred to the microinstruction control register 38 where selected fields of the microinstruction are decoded by decoder 40 to provide the necessary control signals or information to the various subsystems, or components, of a CPU such as CPU 16a.

Referring to Fig. 2, the flow chart of the connect microprogram, the contents of each block identifies the various functions to be performed during a given clock period.

Since processor 16a is a synchronous processor, all functions are synchronized by clock pulses. To avoid unnecessary details, the clock and the conductors that apply the clock signals to the various components of CPU 16a are not shown in Fig. 3.

The operating system initiates the connect microprogram by issuing an instruction in which the operation code designates connect as the function to be performed, and that code is the address of a 32 bit word stored in control unit control store 32. The first 13 bits of that control word are applied to the execution unit control store ECS 34.

The thirteen bits are the address of the first microinstruction of the microprogram, and as a result of them being applied to ECS 34, the first microinstruction of the designated microprogram is transferred to the microinstruction control register 38.

Immediately after the operating system of data processing system 10 transmits a connect instruction to instruction register RBIR 30 of a CPU 16a, a 36 bit data word whose format is as illustrated in Fig. 5B is transferred from an operand buffer, not shown, to the data in register RDI 42 over data bus ZDI 43 through switch ZDI 44. When the first microinstruction 45 of connect has been loaded into the microinstruction control register 38, and during the next clock period, microinstruction 45 will be decoded in the decoder 40 to provide the necessary information and control signals to cause the scratchpad memory SPM 46 to be addressed and the contents of location 07 of SPM 46 to be transferred and stored in register T Base 0 48. This is accomplished by energizing or gating switch RSP 50 so that the signals stored in location 07 of SPM 46 are applied to data bus ZSP-DI 52 by energizing switch ZSP-DI 54 which applies the contents of location 07 of SPM 46 to data bus ZRESB 56, and by energizing switch ZRESB 58 and register T base 0, 48. As a result, the data stored in the location 07 of scratchpad memory 46 is transferred and stored in register T Base 0 48. The information stored in T Base 0 48 is the base address of the reserve memory portion 60 of main memory 22a, which was stored in SPM 46 when data processing system 10 was initialized.

Fig. 4 illustrates the format of the reserve memory segment or portion 60 of main memory 22a. During the execution of the first microinstruction 45, the data word, or operand, of 36 bits, the format of which is illustrated in Fig. 5B, which was stored in the data in register RDI 42 immediately after the connect instruction word had been received by the instruction register RBIR 30, is read out of data in register RDI 42 through switch RDI 62 through shifter 64 which is energized and controlled by the microinstruction to shift to the left by 33 places the informational content of the data word to eliminate any information that might have been placed in the higher order bit positions of the data word. It should be noted that the three bit field represented by bit positions 32 to 35 designate the processor with which the communication is to be established. The output of shifter 64 is stored in temporary register TR 0, 66, which is one of a bank of four such registers, by switch ZSHF 68 being energized by the microinstruction.

At the end of the first microinstruction 45, the base address of the reserve memory segment has been stored in register T Base 0 48, and the three bit field of the data word stored in the data in register 42 which designates, or identifies, the processor to be com municated with, has been shifted to the left so that it occupies the three highest order bit positions 0, 1 and 2 of the data word stored in register TR 0 66.

The next or second microinstruction 69, which is produced as a result of the address of the first microinstruction which is stored in microinstruction register UIC 70 being incremented by 1 by adder 72 and being applied through switch UIC +1, 74 will cause the second microinstruction to be transferred to microinstruction control register 38. During the second clock period, the second microinstruction causes the data out register RADO 76 to have loaded into it a read double command and an address.

The address is generated by the address preparation means illustrated in Fig. 3 which is comprised to carry save adders 78 and 80 and adder 82. The ZX and Z"t inputs to the adder circuit are specified in the microinstruction; bit positions 55 to 57 and 58 to 60. In microinstruction 69 the ZX input is zero and the ZY is 04. The output of the adder 82, which is applied to data bus ASFA 83, is the sum of the base address plus 04, which is the address of the first connect data word in the reserve memory segment which, as illustrated, is located at address location 4 of reserve memory portion 60.

Since a read double command was issued to the main memory controller, MMC, 24a of SIU 12a, the word in location 5, which is the write remote register (WRRR) commuhication command, will also be fetched as a result of the execution of second microinstruction 69.

During the execution of second microinstruction 69, while the address of the first of two words in the reserve section 60 are being generated and the read double command is being issued, the contents of TR 0 66, the three bit field, which now occupies the most significant bit positions, and which identify the processor to be communicated with, is again routed through shifter 64 via switch RTRO-3B 84. Shifter 64 is controlled by microinstruction 69 to shift the data word applied to it to the right 29 positions, which places the three bit field in proper alignment to be added to the base address of the block 86 of connect data words in the reserve memory segment 60 to provide the address of the first of a pair of connect data words associated with and required to communicate with the processor designated by the 3 bit field. The output of shifter 64 is then routed through switches ZSHF 68 so that it is again stored in TR 0 66.

During the third microihstruction 90, which follows the microprogram will wait until the first word is transferred frdm main memory, MM, 22a of SIU 12a into the data in register RDI 42 through switch ZDI 44 from data bus ZDI 43. This first data word, read out of memory in response to the read double command issued to the main memory controller during the execution of the second microinstruction 69, is the contents of address location 4 in the reserve memory section 60 and is the address of the base, or first data word, in block 86 of connect data words locations 50-67 in octal, in Fig.

4.

After the first data word has been read into the data in register RDI 42, the fourth microinstruction 92 will be fetched from the execution control store 34. The contents of RDI 42 are added to the information stored in TR 0 66 and are stored in register TEA0 94. This is accomplished by having the contents of RDI and TR 0 applied to arithmetic and logic unit (ALU) 96 by energizing switch RDI 62 and switch RTRO-3A 98. The output of ALU 96 is stored in the temporary affective address register TEA-0 94 by energizing switch ZALU 100 and switch ZRESB 102. The information stored in register TEA-0 is the sum of the offset of the first of the connect data words with respect to the base of the reserve memory portion 66 (of valve 50 in this example) plus an additional offset to provide the address which corresponds to the processor designated to be communicated with by the three bit field of the data word stored in the data in register RDI 42 at the time the connect microprogram began executing. During the execution of the fourth microinstruction 92, in response to the read double command issued during microinstruction 69, the data word from location 5 in the reserve memory portion 60, which is the write remote register communications command WRRR Corn CMD is read into the data in register RDI 42 through switch ZDI 44.

The fifth microinstruction 104, which follows, causes a read double command to be loaded into the data out register RADO 76 and the address of the first of the two connect data words associated with the processor to be communicated with to be generated by the address generating mechanism of CPU 16. The contents of register T Base 0 48 and TEA-0 94 are applied through switches R Base T 106 and REA-T 108 to carry save adders 78 and 80 and adder 82 to produce the address of the first of the pair of connect data words that provide the necessary information to a main memory controller for it to communicate with the designated processor. It can be seen from Fig. 4 that each pair of connect data words beginning with location 50 and ending with location 57 (in octal) are associated with a designated IOP 14 and that each pair of connect data words beginning with location 60 and ending with location 67 are associated with a designated CPU 16. During fifth microinstruction 104, the contents of the data in register RDI 42 are transferred to and stored in TR 1 66. This is accomplished by energizing switch RDI 110 and switch ZSP-DI 112 to direct the signals for storage in one of the block of temporary storage registers 66, namely TR 1. The data word stored in TR 1 66 is the WRRR communication command, the second data word read out of the reserve memory segment 60 in response to the read double command issued under the control of the second microinstruction 69.

The sixth microinstruction 114, which follows causes the processor 16a to wait until the first word is received from the main memory controller MMCn 24a of main memory 22a of SIU 12a and is stored in data in register 42. When the first connect data word WRRR is received in RDI 42, the seventh microinstruction 116 entered.

The seventh microinstruction causes the first connect data word to be transferred from RDI 42 for storage in temporary register TR 2 66 via the arithmetic and logic unit 96. This is accomplished by energizing switch RDI 118 and switch ZALU 120, which causes the first connect data word to be routed to TR 2. During the seventh microinstruction, the second conncct data word, in response to the issuance of a read double command during the fifth microinstruction 104, is transferred from main memory 22a through the main memory controller MMCn 24a to the data in register RDI 42. Also during the seventh microinstruction 116, the first connect data word is transmitted through ALU 96 so that its contents can be checked to see if all of the bits in the first connect data word are zeroes.

If all bit positions are logical zeroes, test block 122 will produce a logical one signal.

The output of test block 122 is gated through switch ZALUZ=1 124 to go flip flop 126 which is set. Flip flop 126, when set, disables switch 74 and enables switch 128. in initializing the data processing system 10 the presence of logical zeroes in all bit positions of the first connect data word denotes, or represents, that there is no corresponding processor attached to the system.

During the execution of the eight microinstruction. which follows the contents of TR 1, which is one of the group of registers 66, are transferred to the data out register RADO 76. This is accomplished by energizing switch RTR0-3A 98 which causes the signals from TR 1 to pass through ALU 96 and by energizing switch ZALU 100 which will put the contents of TR 1 on data bus ZRESB 56. Energizing switch ZRESB 134 causes the contents of TR 1 to be loaded into register RADO 76. The contents of TR 1 is the write remote register communication command, WRRR, which was fetched from memory and received during microinstruction four.

If the test of the contents of the first WRRR data word discloses that all bit positions were logical zeroes, and, therefore, there was no processor connected to data processing system 10 corresponding to that three bit core or port number, then go flip flop 126 will be set and the switch UIC+l, 74 will be disabled. The branch address switch ECS-BR ADR 128 will be energized.

Microinstruction 138 is then applied to control register 38 and signifies that the processor to be communicated with is nonexistent, or to state it another way, that an illegal port number has been utilized, or an illegal procedure fault has occurred, and the connect microprogram is terminated. (IPR fault occurs).

If the result of the test is negative, then go flip flop 98 does not change state; the microinstruction address in registe nized as such by a main memory controller 24. The command field CMD identifies the type of command to be executed by the main memory controller. The zone field zone is not used, nor is the address field used in the write remote register communications command. The command field for the write remote register command is 1110.

The format of the first of each pair of write remote register data words is illustrated in Fig. 5D. A logical 1 in bit position 3 is the only logical 1 in the first write remote register data word. It is transmitted to an SIU 12 unchanged. If there is no processor corresponding to the number provided in the data word illustrated in Fig.

5D, then all of the bit positions of the first write remote register first data word will be zeroes.

Fig. 5E is the format of the second of each pair of write remote register data words. The field PRO determines whether the communication is with an IOP or a CPU. A logical zero designates that the communication is with an IOP and a logical 1 that the communication is with a CPU.

The field SIU determines which of the two SIU's the processor to be communicated with is attached. The RFU field (reserved for future use) is not used. The field SIU-P identifies the port of the designated SIU to which the message is to be communicated.

In a data processing system 10 the communication functions and operations are specified by the two WRRR data words associated with the WRRR/COMM command. Depending on the command, the two data words contain the specific communication function to be relayed, the destination SIU and port number and the mechanism to be used to signal the presence of the communication at the destination port.

When the main memory controller MMC such as MMCo 24a first receives the WRRR command from SIU 12a, MMCo 24a enters the WRRR/COMM command into its command stack like any other memory command. Based on the contents of bit 1 in the second data word, the two WRRR data words are transmitted over one of two possible data paths to the designated processor.

WHAT WE CLAIM IS: 1. A data processing system comprising: an SIU (system interface unit) having a plurality of ports; a plurality of processing units, including at least one CPU, coupled to respective ports; and at least one main memory coupled to a respective main memory controller in cluded in the SIU, wherein the or each CPU includes means responsive to a connect command includ ing a destination code to - combine the contents of a predeter mined register (reserve memory seg ment base address) with the destina tion code to form a memory address and cause the contents of that address to be read, those contents forming WRRR (write remote register) data in cluding a code identifying an SIU port, - generate a WRRR instruction, and - transmit the WRRR instruction and WRRR data to the SIU.

2. A data processing system according to claim 1 comprising a further SIU having a plurality of ports, a plurality of further processing units coupled to respective ports of the further SIU, and wherein at least one main memory is coupled also to a respective main memory controller in the further SIU.

3. A data processing system according to either previous claim wherein the WRRR instruction and data transmitted to the SIU are forwarded to a main memory controller.

4. A data processing system according to any previous claim wherein the WRRR instruction is stored in the reserve memory segment and is generated by reading it from a predetermined location in that segment.

5. A data processing system according to claim 4 wherein the WRRR instruction includes a further offset which is combined with the combination of the reserve memory segment base address and the destination code to form the main memory address of the WRRR data.

6. A data processing system according to any previous claim wherein the or each CPU includes means for testing the WRRR data to determine whether it indicates that there is no corresponding processor in the system.

7. A data processing system substantially as herein described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. nized as such by a main memory controller 24. The command field CMD identifies the type of command to be executed by the main memory controller. The zone field zone is not used, nor is the address field used in the write remote register communications command. The command field for the write remote register command is 1110. The format of the first of each pair of write remote register data words is illustrated in Fig. 5D. A logical 1 in bit position 3 is the only logical 1 in the first write remote register data word. It is transmitted to an SIU 12 unchanged. If there is no processor corresponding to the number provided in the data word illustrated in Fig. 5D, then all of the bit positions of the first write remote register first data word will be zeroes. Fig. 5E is the format of the second of each pair of write remote register data words. The field PRO determines whether the communication is with an IOP or a CPU. A logical zero designates that the communication is with an IOP and a logical 1 that the communication is with a CPU. The field SIU determines which of the two SIU's the processor to be communicated with is attached. The RFU field (reserved for future use) is not used. The field SIU-P identifies the port of the designated SIU to which the message is to be communicated. In a data processing system 10 the communication functions and operations are specified by the two WRRR data words associated with the WRRR/COMM command. Depending on the command, the two data words contain the specific communication function to be relayed, the destination SIU and port number and the mechanism to be used to signal the presence of the communication at the destination port. When the main memory controller MMC such as MMCo 24a first receives the WRRR command from SIU 12a, MMCo 24a enters the WRRR/COMM command into its command stack like any other memory command. Based on the contents of bit 1 in the second data word, the two WRRR data words are transmitted over one of two possible data paths to the designated processor. WHAT WE CLAIM IS:

1. A data processing system comprising: an SIU (system interface unit) having a plurality of ports; a plurality of processing units, including at least one CPU, coupled to respective ports; and at least one main memory coupled to a respective main memory controller in cluded in the SIU, wherein the or each CPU includes means responsive to a connect command includ ing a destination code to - combine the contents of a predeter mined register (reserve memory seg ment base address) with the destina tion code to form a memory address and cause the contents of that address to be read, those contents forming WRRR (write remote register) data in cluding a code identifying an SIU port, - generate a WRRR instruction, and - transmit the WRRR instruction and WRRR data to the SIU.

2. A data processing system according to claim 1 comprising a further SIU having a plurality of ports, a plurality of further processing units coupled to respective ports of the further SIU, and wherein at least one main memory is coupled also to a respective main memory controller in the further SIU.

3. A data processing system according to either previous claim wherein the WRRR instruction and data transmitted to the SIU are forwarded to a main memory controller.

4. A data processing system according to any previous claim wherein the WRRR instruction is stored in the reserve memory segment and is generated by reading it from a predetermined location in that segment.

5. A data processing system according to claim 4 wherein the WRRR instruction includes a further offset which is combined with the combination of the reserve memory segment base address and the destination code to form the main memory address of the WRRR data.

6. A data processing system according to any previous claim wherein the or each CPU includes means for testing the WRRR data to determine whether it indicates that there is no corresponding processor in the system.

7. A data processing system substantially as herein described with reference to the accompanying drawings.