CA1116261A - Method and apparatus by which one processor in a multiprocessor computer system communicates with another - Google Patents
Method and apparatus by which one processor in a multiprocessor computer system communicates with anotherInfo
- Publication number
- CA1116261A CA1116261A CA287,398A CA287398A CA1116261A CA 1116261 A CA1116261 A CA 1116261A CA 287398 A CA287398 A CA 287398A CA 1116261 A CA1116261 A CA 1116261A
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- register
- data
- address
- data word
- microinstruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
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- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Hardware Redundancy (AREA)
- Computer And Data Communications (AREA)
Abstract
ABSTRACT
A microprogram and apparatus controlled by the microprogram of a data processor obtains the necessary data words, commands and operands, to initiate a communication with another processor of the system, to initiate an action by such other processors in response to the information so communicated.
A microprogram and apparatus controlled by the microprogram of a data processor obtains the necessary data words, commands and operands, to initiate a communication with another processor of the system, to initiate an action by such other processors in response to the information so communicated.
Description
-BACKGP~OUND OF THE INVENTION
Field of the Invention This inven~ion pertains -to electronic data processing systPms. At least some o~ ~he processing units of which are 05 substantially controlled by microprograms. More particularly, this invention relates to a multiprocessor data processing system, and particularly to a microprogram and the apparatus controlled by that microprogram which permits one processor to communicate with another processor of the system to cause the latter processor to in;tiate an action required by the given processor.
Description of the Prior Ar_ In current large computer systems manufactured by the assignee of this application when there is a need for an input/
output operation, hereafter (I/O), a request for such an operation3 sometimes designated as a "connect" instruction is generated by a central processing unit, hereafter ~CPU) under the control of the operating system=of the computer system. The operating system through the CPU in response to the receipt of a connect instruction produces I/O control information identifying a port on a system controller to which the peripheral device to be used in the I/O operation is connected. The system controller generates an interrupt siynal and uses the port number to route the interrupt signal to the processor controlliny the peripheral device. The processor to which the interrupt signal is transmitted in response to its receipt obtains the necessary information to be used in the desired I/O operation from its mailbox, a predetermined location in working store oF the overall system. `;
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In the current data processing systern there are eight - ports on a system controller to which an interrupt signal can - be sent in response to the receipt of a connect cornmand so that a three bit field in a data word can and is used to identify the 05 port of the SCU to which the interrupt is to be sent and the port number thus identifies the processor to which an interrupt - signal is to be directed.
SUMMARY 0~ THE INVENTION
Whenever a manufacturer develops an improved data processing system, one of the requirements frequently imposed on - the design is that it be compatible with earlier systems of that manufacture, i.e., so that programs and, in particular, application programs, which will run on earlier systems, will operate on the improved system without significant reprogramming. Such an improved data processing system has the capability of having up to a maximum of eight processors, I/0 processors and CPU processors, connected into the system, so that a given CPU can communicate with up to eight such processors, since a processor can communicate with itself, in response to the receipt of a conneck instruction in the same format as under prior systems. The improved data processing system, in its maximum configuration, is comprised of ` two system ;nterface units (SIUs) each of which has eight portsto which an I/0 processor or a CPU can be connected. Thus, a three bit field in a data word which was capable in prior data processing systems of uniquely designating the port and thus the ~ processor to which the connect communication to be directed is : no longer sufficient to provide the necessary information required in the new improved data processing system in which this invention is incorporated.
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While the number of processors to which such a communication can be sent eqllals eight, which at least in theory can be uniquely dPscribed by a three bit field; however, since these eight processors can be connected to sixteen diFferent ports 05 in the SIUs and different types of processors, the I/O and the CPUs in the new system requi~re different types of communication signals~ the three bit field of the prior system is no longer adeguate to satisfy the in~ormational requirements to implement the connect instruction in the new improved da~a processing systems.
It is, therefore, an object of this invention to provide `
method and apparatus to permit one processor in an improved mul~iprocessor data processing system to communicate with another in response to an instruction command and a data word supplying information designating the processor to be communicated with, which instruction command and data word are compatible with those used in earlier model computers.
It is another object of this invention to provide a microprogram and apparatus controlled by the microprogram which an originating processor of a multiprocessor data processin~
system in response to khe receipt of a communication request, or connect, command and a data word having a three bit field which designates the processor either an I/O processor or a CPU to which the communication is to be addressed, which produces appropriate data words, commands and operands, so that a main memory contrcller of a designated main memory can communicate ;
with the designated processor to cause that processor ~o init;ate an appropriate program.
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I~ is still another oB~ect o~ t~i~s invention t~ provide a method and apparatus which permits one processor to use this~ method and apparatus to communicate with itself when there i~s a requirement to do so.
Thus, in accordance with one broad aspect of the ~nvention there is prov~ded the method by which a first data processor communi~cates with another data processor in a multiprocessor data procegsing s~stem in response to the ~irst data processor receiving from a mai~n memory controller of a main memory~having a reserve memory segment in which data words are stored in the system, an instruction word directi~ng s~ch a communi~cation) and a first da~a word ~dentifying the processor to Be communi~cated with; compri~sing the steps of:
fetching from a memory the Base address of the reserve memory~ : :
segment of the main memory;
adding to said Base address o~ the reserve memory~segment a f~rst offset to produce a first address;
issuing to the main memory controller a first read command and said first address; :
recei~vi~ng from the main memory controller ~n response to said first read command, a second data word, sai~d second data word Being a
Field of the Invention This inven~ion pertains -to electronic data processing systPms. At least some o~ ~he processing units of which are 05 substantially controlled by microprograms. More particularly, this invention relates to a multiprocessor data processing system, and particularly to a microprogram and the apparatus controlled by that microprogram which permits one processor to communicate with another processor of the system to cause the latter processor to in;tiate an action required by the given processor.
Description of the Prior Ar_ In current large computer systems manufactured by the assignee of this application when there is a need for an input/
output operation, hereafter (I/O), a request for such an operation3 sometimes designated as a "connect" instruction is generated by a central processing unit, hereafter ~CPU) under the control of the operating system=of the computer system. The operating system through the CPU in response to the receipt of a connect instruction produces I/O control information identifying a port on a system controller to which the peripheral device to be used in the I/O operation is connected. The system controller generates an interrupt siynal and uses the port number to route the interrupt signal to the processor controlliny the peripheral device. The processor to which the interrupt signal is transmitted in response to its receipt obtains the necessary information to be used in the desired I/O operation from its mailbox, a predetermined location in working store oF the overall system. `;
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In the current data processing systern there are eight - ports on a system controller to which an interrupt signal can - be sent in response to the receipt of a connect cornmand so that a three bit field in a data word can and is used to identify the 05 port of the SCU to which the interrupt is to be sent and the port number thus identifies the processor to which an interrupt - signal is to be directed.
SUMMARY 0~ THE INVENTION
Whenever a manufacturer develops an improved data processing system, one of the requirements frequently imposed on - the design is that it be compatible with earlier systems of that manufacture, i.e., so that programs and, in particular, application programs, which will run on earlier systems, will operate on the improved system without significant reprogramming. Such an improved data processing system has the capability of having up to a maximum of eight processors, I/0 processors and CPU processors, connected into the system, so that a given CPU can communicate with up to eight such processors, since a processor can communicate with itself, in response to the receipt of a conneck instruction in the same format as under prior systems. The improved data processing system, in its maximum configuration, is comprised of ` two system ;nterface units (SIUs) each of which has eight portsto which an I/0 processor or a CPU can be connected. Thus, a three bit field in a data word which was capable in prior data processing systems of uniquely designating the port and thus the ~ processor to which the connect communication to be directed is : no longer sufficient to provide the necessary information required in the new improved data processing system in which this invention is incorporated.
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While the number of processors to which such a communication can be sent eqllals eight, which at least in theory can be uniquely dPscribed by a three bit field; however, since these eight processors can be connected to sixteen diFferent ports 05 in the SIUs and different types of processors, the I/O and the CPUs in the new system requi~re different types of communication signals~ the three bit field of the prior system is no longer adeguate to satisfy the in~ormational requirements to implement the connect instruction in the new improved da~a processing systems.
It is, therefore, an object of this invention to provide `
method and apparatus to permit one processor in an improved mul~iprocessor data processing system to communicate with another in response to an instruction command and a data word supplying information designating the processor to be communicated with, which instruction command and data word are compatible with those used in earlier model computers.
It is another object of this invention to provide a microprogram and apparatus controlled by the microprogram which an originating processor of a multiprocessor data processin~
system in response to khe receipt of a communication request, or connect, command and a data word having a three bit field which designates the processor either an I/O processor or a CPU to which the communication is to be addressed, which produces appropriate data words, commands and operands, so that a main memory contrcller of a designated main memory can communicate ;
with the designated processor to cause that processor ~o init;ate an appropriate program.
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I~ is still another oB~ect o~ t~i~s invention t~ provide a method and apparatus which permits one processor to use this~ method and apparatus to communicate with itself when there i~s a requirement to do so.
Thus, in accordance with one broad aspect of the ~nvention there is prov~ded the method by which a first data processor communi~cates with another data processor in a multiprocessor data procegsing s~stem in response to the ~irst data processor receiving from a mai~n memory controller of a main memory~having a reserve memory segment in which data words are stored in the system, an instruction word directi~ng s~ch a communi~cation) and a first da~a word ~dentifying the processor to Be communi~cated with; compri~sing the steps of:
fetching from a memory the Base address of the reserve memory~ : :
segment of the main memory;
adding to said Base address o~ the reserve memory~segment a f~rst offset to produce a first address;
issuing to the main memory controller a first read command and said first address; :
recei~vi~ng from the main memory controller ~n response to said first read command, a second data word, sai~d second data word Being a
2~ second of~set from tHe base address o~ the reserve memory segment, recei~ing from the main memory~controller a third data word ~n . ~
response to said fi~rst read command said thl~d data word ~eing a ~ri~te remote register command; ;~
addi~g to the Base addTess o~ tHe reserve memory~, ~he second off~
set and tHe i~dent~fi~cation o~ the proces~sor to Be communi~cated w~th from sai~d fi~st data word ~o produce a second address i~n the reserve memory segment at whl`ch address the fi~rs* of two connect da~a words needed to complete the communi~cation w~th the proces~sor to ~e communi~cated with are .
stored;
i~suing to the main memory~controller a second read dou~le command ,;
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and the second address;
receiving from memory in response to said second read command a first connect data word;
testing to see if the first connect data word is valid;
terminating the method i the said first data word is not valid; or transmitting to the main memory controller, the write remote regis~er command, the first connect data word, and the sec~nd connect data word; and terminating the method.
In accordance with another broad aspect of the in~ention there ; ~g prov~ded apparatus by which a first data processor communicates withanother data processor in a multipr~cessor data processing system in response to the ~irst data processor receiving from a main memory controller of a main memory o~ the system an instruct~on word directing such a communicat~on and a first data word identifying the processor to be communicated with, said main memory having a main memory segment i~n which data words are stored, comprising;
means ~OT fetching from a memor~, t~e ~ase address o~ the reserve : :.
memory~segment of the main memory;
means or adding to said ~ase address a firs* offset to produce a irst address;
means for issuing to the mai~n memory contr~ller a f~rst read : ~.
command and said irst address;
means for receiving ~rom the main memory~colltroller in response to said first read command a second data word, said sec~nd data word Being a seeond o~fse.t rom the ~ase address o~ ~he reserve memor~ segment, a~d .~r storing sai~d ~irst data word;
: means ~r recei~ng ~ro~ the ma~n memory~controller a third data word ~n respons~e to s~ai~d fi~rst read command, sa~d t~ird data word bei~ng a 3Q write remote register comma~d, and storing said second data word;
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s ; means for add~ng the base address o~ the reserve memory segment and the second offset from the base address o~ the reserve memorr segment ., received in response ~o the ~rst read command, and the ldentification of . the processor to be communicated ~th from said first data word to produce ; a second address in the reserve memory segment, said address being the location in the reserve memory segment ~here the first of two connect data words needed by the main memory controller to complete the communication with the processor to be communicated w~th are stored;
means for issuing to the ma~n memory controller a second read command and the second address; .
means for receiving from the main memory controller in response to sa~d second read command a first c~nnect data word and storing said ~rst connect data word;
means for receiving ~rom memory in response to said second read command, a second connect data word and storing said second connect data word;
means for testing the f~rst connect data word received to deter-mine if ~t is vali~d;
means f~r term~nat~ng th~ commun~cat~on i~ the said first connect data word is not valid; and means for ~ssuing the mai~n memory controller the wri~te remote reg~ster command, the $~rst connect data word, and the seccnd connec~ data word.
Accord~ng to another broad aspect o~ t~e inventi~on there ~g pro~
~ded, ~n a data proce5s-ing system hav~ng a data processor a main memory and a ma~n memory~controller;
sai~d data processor having a scratchpad memory7 a ~hiter, swi~tches~
arithmetic. and logic unit, adders and a plural~t~ of registexs including a data ~n register and an instructi~on regi~ster, sai~d instruct~on register responsi~e to t~e recelpt o a connect i~nstruct~on word from~a main memory : ~5~_ via a main memory controller ~ni~ti~ati~ng a mi~croprogram to accomplish the instruction; said m~croprogram compris~ng the steps of:
obtaining from the scratchpad memory of said processor a flrst address, said first address being the address of the base o~ a reserve memory segment of a main memory, s~or~ng said first address in a first temporary aase register, shifting a predetermined number of bit positions to the left, a first data word stored in the data in register of said processor, said data word designating a processor of said data processing system to be communicated with; and storing the first data word after belng 10 shifted in a first temporary reglster;
` generating a second address by adding a predetermined number to f t~e first address and issuing a ~irst read double command and the second ~: address to the main memory controller of the main memory;
shifting the first data word stored in said first temporar~ base register 29 bit positions to the right and storing said f~rst data word after being shifted in said first temporary register;
waiting until in response to the issuance of said first read ~` double command a second data word is stored in the data in regi~ster said second data word being the offset to the base address of the reser~e memory segment o~ a plurality of connect data words, adding to the second data word the data word stored in said ~Irst temporary register and storing the sum in a temporary address reglster; and receiving in the data in register ~n response to the first read double . command a third data word; said third data word being a write remote regis-ter communications command;
adding the contents of said first temporary~base register and said temporary address register to produce a third address, said third address be~ng the address in the reserve memory segment o~ the first o~' a palr of connect data words, said connect data words providing informati~on necessary ; 30 to cause the main memory contr~ller to communicate with the designated ' . ~
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processor; i~ssuing a second read double cammand and sa~d third address to the main memory controller o~ the main memory; storing the third data word, the write remote register command in a second temporary register;
waiting until the first connect data word is received by the data in register in response to said second read double command;
transferring the first connect data word to a third temporary register; receiving the second connect data word into the data in register in response to said second read douale command; and checking the first connect data word to determine if all bit positions are zeroes;
terminating the microprogram if all ~i~ positions of the first connect data word are zeroes;
and if all bit positions o~ the first connect data word are not zeroes;
issuing to the main memory controller the write remote regi~ster command, the first connect data word, the second word of connect data and terminating the microprogram.
rn ~ecordanee w~th another broad aspec* of t~e invention there is provided, in a data processing system ha~ing a data processor; said pro- :
cessor having a temporary base register, temporary registers, arithmetic logic units, temporary address registers, instruction register and a data in register said instruction register responsive to the receipt o$ a connect i~nstruetion from a main memory ~ia a main memory~ eontroller ~n~tiating a microprogram stored in an execution control store o~ the processor to cause predetermined data words to be communicated to a processor o said system, the processor to ~e communicated with being designated b~ a first data word stored in the data in register; the improvements comprising: ' means responsi~e to the first microinstruction of said mi~croprogram ~:
or obtaining from a scratchpad memory of said processor the address of the base of a reserve memory segment o a main memory and for storing said address in a temporary base register; means for shiting a predetermined ~, r5d-' ' `-" ~.gL6;;~6~
;` number of bit positions to the left the first data word stored in sald data in register; and for storing the data word aeter being shifted in a ~irs~
- temporary register;
means responsive to the second microi~nstruction o~ said micropro-gram for adding a predetermined numaer to the address of the base of the reserve memory segment stored in the temporary base register to produce a first address in the reserve memory segment of said main memory and for issuing a first read double command to the main memory controller of the main memory and said first address; the data words fetched from main memory in response to the first read double command being a second and a third data word, said second data word being the offset from the base address of a block of connect data words and the third data word be~ng a write remote register communication command; and means for shifting a predetermined nu~ber of bit positions to the right the ftrst data word stored in said fiTst temporary regi~ster and storing sa~d ~irst data word after being shifted in said first temporary regi~ster, means responsive to the third microinstruction of said micropro- :`
gram for storing in the data in regi~ster said second data word;
means responsive to the fourth m~croinstruct~on of sa~d micropro-~0 gram for adding to the second data word the data word stored in said first temporary register and storing the sum in a temporary address register and for storing the third data word in the data in register, means responsive to the fi~th microi`nstruction of the micropro-gram for adding the contents of the temporary address regis*er and said temporary base register to produce a second address in the reserve memory segment, said second address being that o~ the first o~ a pair of connect ~ -data words, said connect data words providing in~ormation to the main memory controller to cause said controller to communicate with the designated processor; for issuing a second read double command to the main memoTy controller of the main memory and said second address, and for storing the -Se~
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t~ird data word in a second t~mporary regist~r~
means responsive to the six~h microinstruction of said micropro-; gram for receiving in the data in register the firs~ word of connect data;
means responsive to the seventh microinstruction of sa~d micropro-gram or storing the first connect data word in a third temporary register, for storing the second connect data word in the data in register; and for checking the first connect data word to determine if all lts blt positions are zeroes;
means responsive to the eighth micro~nstruction of the micropro-gram for terminating the microprogram if all ~it positions of the first connect data word are zeroes; and if the test indicates that the ~irst connect data word ls not all zeroes, means responsive to a ninth, tenth, and eleventh microlnstruction for issuing to the main memory controller the write remote register command, the first word of connect data, the second word of connect data, and for terminating the microprogram.
The-above and other o~ects of the invention, together with features and advantages thereof will become apparent from the following detailed description of a preferred embodiment of the ~nvention when consid-ered in conjunction with the attached drawings.
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Pig. 1 is a block diagram of an improved mult~processor data processing system, the CPU's of which ~ncorporate my invention.
Fig. 2 is a flow chart of tTIe connect microprogram, - Fig. 3 is a block diagram of the components of a CPU which, in ; response to control signals derived from t~e ~croprogram, initiate communication with another processor of the system.
Fig. 4 is the format of a part o~ ~he reserve memory portion of a main memory of the computer system.
~ig. 5 is the format of instruction words and data words used in ~5~-: . ;
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the data processing system o~ ~ig. 1.
~ig. 6 is the format o~ the microinstructions used ln the connect microprogram. -~
-~ Fig. 7 is the ~ormat of the control un~t control store data word.
Flg. 1 is a ~lock diagram o~ a maxlmum c~n~igurat~on wlth respect to processors of an improved da~a processing system 10 in which the present in~ention is incorporated. Data processing system 10 has two SIU's 12a and 12~. Each SIU 12 has 15 ports identi~ied ~y letters A through K plus four additional memory ports~ local memory-port 0, (LMa)~ local memory port 1, CLMl~ ~
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and two main memory ports in which the main memory control function or con-trollers (MMCo) and ~MMC1) are located. On certain pairs of ports such as G and H and ports E and F, a pair of locked I/O processors (IOP/P) 14a, 14b, 14c 14d can b~ attached.
OS Up to four central processing units (CPUs) 16a, 16b, 16c and 16d, two to each SIU can be attached to any two of ports A, B, C, D, E, F, G, or H of each SIU. Local memories (LMo) 18a, 18c or (LM1) 18b, 18d can be connected to local memory ports (LMo) 20a, 20c and (LM1) 20b, 20d of each SIU 12 and a main memory (MMo) 22a, 22c and (MM1) 22b, 22d can be connected to the main mernory controller MMCo 24a, 24c and MMC1 24b, 24d of the SIU's 12a and 12b. Each of the main memory controllers MMCo 24a, 24c or MMC1 24b, 24d of the SIU's 12a, 12b has two ports and each of the main ; memories 20a and 20b also has two ports which are cross-connected to permit communication to occur between devices and memories , attached to the respective SIU's 12.
Each of the main memory controllers MMCo 24a, 24c, MMC
24b, 24d of SIUs 12a, 12b in addition to writing data into a main memcry MMo 221, 22c, or MM1 22b, 22d and to reading data out of an MMo or MM1, also has certain communication control functions.
Communications between SIU's can be from a main memory controller such as MMCo 24a of SIU 12a to the main memory MMo 22c of SIU 12b. MMo 22c communicates or transmit the message to its main memor~ controller MMCo 24c of SIU 12b. MMCo 24c in turn directs the communication to the designated port of SIU 12b to which is attached a processor such as IOP/P 14c or CPU 16c, for example, of SIU 12b the processor to which the communication is directed.
' - ~ . .;; : - :: , A CPU such as 16a in the course of performing an application program, ~ill reach a point where an I/O operation is required either to bring in From d peripheral device data stored on the peripheral device or to read out from memory 05 information to be -transferred to a peripheral deYice. When the need for an I/O operation occurs, or more broadly~ whenever one processor needs to communicate with another processor including itself, the operating system of data processing system 10 will cause an instruction to be transm;tted to a CPU such as 16a for example. The contents of the operational field of the instruction word is such as to indicate or designate that a specific type of communication is to be performed or executed. The operating system will also provide 16a a data word~ a certain designated field of ~hich will identify the processor to which the ` 15 communication is to be sent. The details of the apparatus and i method to do this will be more fully~described later.
The field identifying the processor is a three bit field located in the lowest order positions of the operand, or data word. Fig. 5B illustrates the format of such a data word with the field identifying the processor occupyîng bit positions 33-35.
It can be seen3 however, from Fig. 1 that it is possible to connect up to four processors to each of two SIU's 12a, 12b which processors can be connected to various ports so that the necessary information needed to uniquely identify CPU 16b or IOP/P
14d, for example, to which the communication is to be sent canno~
be adequately specified by a three bit field. Thus, additional information is required. The additional information required is stored in a reserve memory portion of main memory such as MMo 22a of SIU 12a. The reserve memory portion illustrated in Fig. 4 of a main memory is a con~inguous block of memory~ whose position ~7-- : . ,; . . . ;. . .. .
in main memory 22a and the data words stored therein is established at the time data processing system 10 is initialized prior to beginning~?processing of application programs.
To perform the connect function, the processor has to 05 generate the addresses in the reserve memory to fetch the necessary information so that SIU 12a can steer the communication to the correct processor on the correct SIU 12 as well as -to provide that processor with the correct signals to cause it to initiate the desired function. In addition it is necessary for CPU 16a to retransmit or issue to the main memory controller MMCQ
24a of SIU 12a this information. Main memory controller MMCo 24a of SIU 12a then provides the necessary signals in the form of data words to be transmitted by SIU 12a to the addressed processor.
Main memory controller 24a will recognize the communication command and the data words transmitted to it as requesting special handling As a result, main memory controller 24a causes the necessary ~-communication signals and information to be transmitted to the desi~nated IOP/P or CPU either directly, if the designated processor is connected to the same SIU to which the main memory controller receiving the connect command is connected or, through a corresponding main memory 22c and main memory controller 24c of SIU 12b if the processor to be communicated with is attached to a port of SIU 12b. As a result of the information and signals transmitted to the designated processor, that processor knows that it is being requested to do something, and is provided with the necessary information requried by the designated processor to perform the desired function whether it is an I/O function, such as is typically provided by an IOP/P, or some other type of function which may be performed by a CPU.
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Fig. 2 is a flow chart of the connect microprogram identifying each of the microinstructions of the microprogram that is executed by a CPU's execution unit in executing the connect microprogram. Fig. 3 is a block diagram of the hardware 05 elements of a CPU 16 which are utilized in the performance of the - connect microprogram. The connect instruction is received from an instruction buffer, which is not illustrated, over the instruckion buffer bus ZIS 26 from main memory controller such as MMC0 24a and is transmitted through ZI8 switch Z8 to RBIR 30 for storage therein. Fig. 5A is the format for an instruction word with the ten bit field, bit locations 18-279 being the operation code~
The operation code of an instruction word is the address in the control unit control store (CCS~ 32 of a control unit control word the format of which is illustrated in Fig. 7.
~ 15The control unit control store word stored in CCS 32 is `~ comprised of 32 bits. The thirteen bit field consisting of bit positions 0 through 12 is the address of the starting location for the microprogram specified by the operation code of the instruction stored in the instruction register RBIR 30 or the address of the initial microinstruction of the microprogram.
When the op code, from an instruction, is applied to the CCS 32 from RBIR 30, the control unit control word stored at the address corresponding to the op code, the contents of bit position 0 through 12 will be applied to the execution control store (ECS) -34 through switch CCS-ADR 36. The receipt of the address of a microinstruction by ECS 34 causes the microinstruction stored at that address to be transferred to the microinstruction control register 38 where selected fields of the microinstruction are decoded by decoder 40 to provide the necessary control signals or information to the various subsystems, or components, of a . .
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CPU such as CPU 16a, for example as will be more flIlly described later.
Referring to Fig. 2, the fIow chart of the connect microprogram, the contents of each block identifies the various 05 functions to be performed during a given clock period. Since processor 16a is a synchronous processor, all functions are synchronized by clock pulses as is well known in the art. To avoid providing unnecessary details, the clock and the conductors that apply the clock signals to the various components of CPU
16a are not illustrated in Fig. 3.
The operating system initiates the connect microprogram by issuing an instruction in which the operation code designates connect as the function to be performed and that code is the address o~ a 32 bit word stored in control unit control store 32.
The first 13 bits of that control word, the format of which is illustrated in Fig. 7, are applied to the execution unit control .
store ECS 34. The thirteen bits are the address of the first ~ -microinstruction of the microprogram, and as a result of there ; being applied to ECS 34, the first microinstruction of the ;~ designated microprogram is transferred to the microinstruction control register 38. `
Immediately after the operating system of data processing system 10 transmits a connect instruction to instruction register RBIR 30 of a CPU 16a, a 36 bit data word whose format is as illustrated ;n Fig. 5B is trans~erred from an operand buffer, which is not illustrated, to the data in register RDI 42 over data bus ZDI 43 through switch ZDI 44. When the first microinstruction 45 of connect has been loaded into the microinstruction control ~`
register 38, and durîng the next clock period, microinstruction 45 will be decoded in decoder 40 to provide the necessary ;
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information and con~rol signals to cause the scratchpad memory SPM 46 to be addressed and the con~ents of location 07 of SPM
46 to be transferred and stored in register T Base 0 48. This iâ accomplished by energi~ing or ~ating switch RSP 50 so that ~ 05 the signals stored in location 07 of SPM 46 are applied to data `- bus ZSP-DI 52 by energizing switch ZSP-DI 54 which applies the contents of location 07 of SPM 46 to data bus ZRESB, 56 and by energizing switch ZRESB 58 and register T Base 0 48. As a result, the data stored in the location 07 of scratchpad memory 46 is transferred and stored in register T Base 0 48. The ~` information stored in T Base 0 48 is the base address of the reserve memory portion 60 of main memory 22a, for example, which ,~ was stored in SPM 46 when data processing system 10 was initialized.
~ig. 4 illustrates the format of the reserve memory segment or portion 60 of main memory 22a, for example. During the execution of the first microinstruction 45, the data word3 or operand, of 36 bits, the format of which is illustrated in Fig.
5B, which was stored in the data in register RDI 42, immediately after the connect instruction word had been received by the instruction register RBIR 30, is read out of data in register RDI 42 through switch RDI 62 through shifter 64 which is `
energized and controlled by the microinstruction to shift to~the left by 33 places the informational content of the data word to eliminate any information that might have been placed in the higher order bit positions of the data word. It should be noted that the three bit field represented by bit positions 32 through 35 designate the processor with which the eommunication îs to be established. A preferred embodiment of shifter 64 embodiment is disclosed in application Serial No. 559,115 filed March 17, 1975 entitled Data Alignment Circuit and is assigned to the same - 1 1 - : :
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assignee~as this application, ~herefore, its details are not illustrated. The output of shifter 64 is stored in teMporary register TR 0 66, which is one of a bank of four such registers, by switch ZSHF 68 being eneryized by the microinstruction.
05 At the end of the first microinstruction 45, the base ~ address of the reserve memory segment has been stored in register T Base Q 48, and the three bit field of the data word stored in the data in register 42 which designates, or identifies, the processor to be communicated with, has been shifted to the left so that it occup;es the three highest order bit positions 0, 1 and 2 of the data word stored in register TR 0 66.
The next or second microinstruction 6~, which is produced as a result of the address of the first microinstruction which is stored in microinstruction register UIC 70 being incremen~ed lS by 1 by adder 72 and being applied through switch UIC+l, 74 ~;
wi71 cause the second microinstruction to be transferred to microinstruction control register 3$~ During the second clock period, the second microinstruction causes the data out register -`
RAD0 76 to have loaded into it a read double command and an ` 20 address.
The address is generated by the address preparation means illustrated in Fig. 3 which is comprised of carry save adder 78, carry save adder 80 and adder 82. The construction of adders 78, -80 and 82 is conventional and well known in the art and is, therefore, not illustrated in further detail. The ZX and ZY
- inputs to the adder circuit are specified in the microinstruction;
i.e., bit positions 55 through 57 and 58 through 60 of the ~ ~-microinstruction, see Fig. 6 for the format of a microinstruction.
In microinstruction 69 the ZX input is zero and the ZY is 04.
The output of the adder 82 which is applied to data bus ASFA 83, .:
which is the sum of the base address plus 04, is the address oF
f the first connect data word in the reserve memory segment which, as illustrated, is located at address location 4 of reserve memory portion 60.
05 Since a read clouble command was issued to the main memory controller, MMCo 24a of SIU 12a the word in location 5, which is the write remote register (WRRR~ communication command will also ~ be fetched as a result of the execution of second microinstruction `. 6g.
Dur;ng the execution of second microinstruction 69, while the address of the first of two words in the reserve section 60 are being generated and the read double command is being issued, the contents of TR 0 66, the three bit field, which now occupies the most significant bit positions; and which identify the : 15 processor to be communicated with, is again routed th~ough shifter 64 through switch RTR0-3B 84 and shifter 64 is con~rolled by microinstruction 69 to shift the data word applied to it to the right 29 positions which places the three bit field in proper alignment to be added to the base address of the block 86 of connect data words in the reserve memory segment 60 to provide the address of the first of a pair of connect data words associated with and required to communicate with the processor designated by the 3 bit field. The output of shi~ter 64 is then routed through switches ZSHF 68 so that it is again stored in TR 0 66.
During the third microinstruction 90, which is fetched from the execution unit control store 34 as a result of the address of ` .
the previous microinstruction being incremented by one and being : applied to ECS 34 through switch 74, the microprogram will wai~
until the first word is transferred from main memory, MMo ?2a of SIU 12a into the data in register RDI 42 through switch ZDI 44 .~ , .
~6~L, from data bus ~DI 43. This f;rst data word, read out oF memory in response to the read double command issued to the main memory controller during the execution of the second microinstruc~ion 69, is the contents of address location four in the reserve memory -- 05 section 60 and is the address of the base, or first data word, in block 86 of connect data words locations 50-67 in octal, in Fig. 4.
After the first data word has been read into the data in register RDI 42, the fourth microinstruction 92 will be fetched from the execution control store 34. The contents of RDI 42 are added to the information stored in TR 0 66 and are stored in register TEA-0 94. This is accomplished by having the contents of RDI and TR O applied to arithmetic and logic unit (ALU) 96 by energizing switch RDI 62 and switch RTRO^3A 98. The output of ALU 96 is stored in the temporary affective address register `:
TEA-O 94 bt energizing switch ZALU 100 and switch ZRESB 102.
The information stored in register TEA-0 is the sum of the offset of the first of the connect data words with respect to the base of the reserve memory portion 66, 50 in the example illustrated, ~` 20 plus an additional offset to provide the address which corresponds to the processor designated to be communicated with by the three bit field of the data word stored in the data in register RDI 42 at the time the connect microprogram began executing. During the .
execution of the fourth microinstruction 92, in response to the -.
read double command issued during microinstruction 69, the data ~ :
word from location five in the reserve memory portion 60 the ~ write remote register communications command WRRR Com CMD is read : into the data in register RDI 42 through switch ZDI 44. At the completion of the fourth microinstruction 92, the address in ~; 30 microinstruction register 70 is incremented by one by adder 72 and . ~
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and the address of the ~ifth microinstruction 104 is applied to the execution control store 34 and the fifth microinstnuction is then transferred from control store 34 to microinstruction control register 38.
05 During the clock period associated wTth the fifth microinstruction 104, the fifth microinstruction 104 causes a read double command to be loaded into the data out register RADO
76 and the address of the first of the two connect data words associated with the p,rocessor to be communicated with to be generated by the address generat;ng mechanism of CPU 16. The contents of register T Base O 48 and TEA-O 94 are applied through switches R Base T 106 and REA-T 108 to carry save adder 78 and 80 and adder 82 to produce the address of the first of the pair of connect data words that provide the necessary informatîon to a main memory controller for it to communicate with the designated processor. It can be seen from Fig. 4 that each pair of connect data words beginning with location 50 and ending with location 57 in octal are associated with a designated IOP/P 14 and that each pair of connect data words beginning with location 60 and ending with location 67 are associated with a designated CPU 16.
During fifth microinstruction 104, the contents of the data in register RDI 42 are transferred to and stored in TR 1 66. This is accomplished by energizing switch RDI 110, and switch ZSP-DI ' -~
112 to direct the signals for storage in one of a block of temporary storage registers 66, particularly TR 1. The da~a word stored in TR 1 66 is the WRRR communication command, the second data word read out of the reserve memory segment 60 in response to the : read double command ;ssued under the control of the second microinstruction 69.
,.
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The sixth microinstruction 114, which is the result of incrementing the microinstruction stored in register 70 by one, causes the processor 1~a to wait until the first word is received from the main memory controller MMCo 24a of main memory 22a of 05 SIU 12a and is stored in data ;n register 42. When the first connect data word WRRR is received in RDI 427 the microinstruction - address stored in register 70 is incremented by one and the seventh microinstruction 116 is transferred to the microinstruction control register 38. The seventh microinstruction causes the first connect data wGrd to be transferred from RDI 42 for s~orage in temporary register TR 2 66 via the arithmetic and logic unit 96. This is accomplished by energizing switch RDI 118 and switch - ZALU 120, which causes the first connect data word to be routed to TR 2. During the seventh microinstruction, the second connect data word, in response to the issuance of a read double command during the fifth microinstruction 1043 is transferred from main memory 22a through the main memory controller MMCo 24a tG the data in register RDI 42. Also during the seventh microinstruction 116, the first connect data word, as pointed out above, is `~-transmitted through ALU 96 so that its contents can be checked to see if all of the bits in the first connect data word are zeroes. If all bit positions are logical zeroes, test block 122 will produce a logical one signal. The output of test block 122 is gated through switch ZALUZ=1 124 to go flip flop 126 which is set. Flip flop 126, when set, disables switch 74 and enables switch 128. In initializing the data processing system 10 the presence of logical zeroes in all bit positions of the firstl ~ -connect data word denotes, or represents, that there is no corresponding processor attached to the system.
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The address of microinstruction 116 stored in register 70 is incremented by one and the eighth microinstruction 130 is transferred to the microinstruction control register 34. During the execution of the eighth microinstruction, the contents of TR 1, 05 which is one of a group of register 66, ;s transferred to the data out register RAD0 76. This is accomplished by energizing switch RTR0-3A 98 which causes the signals from TR 1 to pass through ALU 96 and by the energizing switch ZALU 100 which will put the contents of TR 1 on data bus ZRESB 56. Energizing switch ZRESB 134 causes the contents of TR 1 to be loaded into register RAD0 76. The contents of TR 1 is the write ~emote register communication command, WRRR, which was fetched from memory and received during microinstruction four.
If the test of the contents of the first WRRR data word discloses that all bit positions were logical zeroes, and, `~ therefore, there was no processor connected to data processing system 10 corresponding to that three bit code or port number, then go flip flop 126 will be set and the switch UIC+1, 74 will be disabled. The branch address switch ECS-BR ADR 128 will be energized. Microinstruction 138 is then applied to control register 38 and signifies that the processor to be communicated with is nonexistent, or to state it another way, that an illegal port number has been utilized, or an illegal procedure fault has occurred, and the connect microprogram is terminated. (IPR fault occurs.) If the result of the test is negative, then go flip flop 98 does not change state, the microinstruction in register 70 is incremented by one so that the ninth microinstruction 136 will be applied to the control register 38. The ninth microinstruction 136 causes the contents of RAD0 76 to be issued to the memory controller MMCo 24a of SIU 12a.
~` :
.
The tenth microinstruction 140 is produced at the next clock pulse as a result of the address of the ninth microinstruction in register 70 being incremented by one and being applied to the execution control store 32 through switch 74. The tenth 05 microinstruction causes the contents of TR 2 to be transferred to the RAD0 76, the routing being the same as that which caused the ! WRRR command to be transferred from TR 1 to RAD0 76. The data word stored in the data out register RAD0 76 is the first connect data word that was read out of the reserve portion 60 of main memory 22a, and which was received ~uring the sixth microinstruction 114. This word is also issued to the MMCo 2~a of SIU 12a. The microinstruction in register 70 is incremented by one and tbe address o~ the eleventh microinstruction 142 is applied to the ECS 34. The eleventh microinstruction is applied to control register 38 and causes the contents of RDI 42 to be transferred to RAD0 76. This is accomplished by energizing switch RDI 110, '.
switch ZSP-DI 54 which connects the contents of register RDIl42 onto data bus ZRESB which is then switched into RAD0 7~ through switch ZRESB 134. This is the second word of connect data which is then issued to MMCo 24a of SIU 12a. The eleventh microinstruction being the last microinstruction of the connect microprogram also causes the connect microprogram to terminate.
The format of the microins~ruct;on for CPU 60, particularly the fields relevant to the connect instruction, is illustrated in Fig. 6. The field EUFMT (2:1) defines the format of the ;
microinstruction from bit 0 through bit 31. For all microinstructions of the connect microprogram EUFMT is a logical 1.
.
`, The ~ield TR for Temporary Register write control (3:3) ' controls or determines into which of four rec~isters constitutin~
! a bank of re~isters identified as TR 66 a data word is to be ', temporarily stored. The following table determines the TR
registers into which a data word is to be s-torqd:
i O.YX No change .~ lOO Write TR-O
, - lOl Write TR-l .l llO Write TR-2 I~) 1].1 Write TR-3 The Z0PA field (9:4~ selects the output of the Z0PA
switches to be applied to the Z0PA data bus 144. The following table shows the relationship between the contents of the Z0PA
~ field and the outputs of the Z0PA data bus 144 that are relevant j 15 - to the connect instruction:
. ~) 0000 TR-O
', 1) OOO1 TR-l . ~
2) OOlO TR-2 ~ 3) OOll TR-3 i 2n 8-11) lOXX RDI
, 15) 1111 O (disable) ~ The Z0PB field (13:4) selects the output of the Z0PB
,j switches to be applied to the Z0PB data bus~146. The following I table sets forth the relationships between the conte.nts of the .~ 25 Z~P~ field and the source of the signals on the Z0PB data bus 146:
i O) OOOO TR-O
s~ 1) OOOl. TR-l ' ~ 2) OOlO TR-2 ~ 3) OOll TR-3 ¦ 31! 8-11) lOXX ~ RDI
~ 15) 1111 O (disable) ! -19-The ~ield %RESA (17:2) selects the output of the ZRES~
switches to be appl.ied to the ZRESA data bus 148. The following table sets forth the relationship between the contents of the %RESA field and the source of the signals on ZRESA data bus 148:
01 Shifter 10 Scratchpad/RDI switch I The field ZRESB (19:2) selects the output of the ZRESB
I switches to be applied to the ZRESB data bu~ 56. The following table sets forth the relationship between the contents of the I ZRESB fielcl and the source of the signals on the ZRESB data bus ~ 56:
¦ 00 ALU
~ 01 Shifter
response to said fi~rst read command said thl~d data word ~eing a ~ri~te remote register command; ;~
addi~g to the Base addTess o~ tHe reserve memory~, ~he second off~
set and tHe i~dent~fi~cation o~ the proces~sor to Be communi~cated w~th from sai~d fi~st data word ~o produce a second address i~n the reserve memory segment at whl`ch address the fi~rs* of two connect da~a words needed to complete the communi~cation w~th the proces~sor to ~e communi~cated with are .
stored;
i~suing to the main memory~controller a second read dou~le command ,;
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and the second address;
receiving from memory in response to said second read command a first connect data word;
testing to see if the first connect data word is valid;
terminating the method i the said first data word is not valid; or transmitting to the main memory controller, the write remote regis~er command, the first connect data word, and the sec~nd connect data word; and terminating the method.
In accordance with another broad aspect of the in~ention there ; ~g prov~ded apparatus by which a first data processor communicates withanother data processor in a multipr~cessor data processing system in response to the ~irst data processor receiving from a main memory controller of a main memory o~ the system an instruct~on word directing such a communicat~on and a first data word identifying the processor to be communicated with, said main memory having a main memory segment i~n which data words are stored, comprising;
means ~OT fetching from a memor~, t~e ~ase address o~ the reserve : :.
memory~segment of the main memory;
means or adding to said ~ase address a firs* offset to produce a irst address;
means for issuing to the mai~n memory contr~ller a f~rst read : ~.
command and said irst address;
means for receiving ~rom the main memory~colltroller in response to said first read command a second data word, said sec~nd data word Being a seeond o~fse.t rom the ~ase address o~ ~he reserve memor~ segment, a~d .~r storing sai~d ~irst data word;
: means ~r recei~ng ~ro~ the ma~n memory~controller a third data word ~n respons~e to s~ai~d fi~rst read command, sa~d t~ird data word bei~ng a 3Q write remote register comma~d, and storing said second data word;
i, ., ~, ~5a- ~ .
s ; means for add~ng the base address o~ the reserve memory segment and the second offset from the base address o~ the reserve memorr segment ., received in response ~o the ~rst read command, and the ldentification of . the processor to be communicated ~th from said first data word to produce ; a second address in the reserve memory segment, said address being the location in the reserve memory segment ~here the first of two connect data words needed by the main memory controller to complete the communication with the processor to be communicated w~th are stored;
means for issuing to the ma~n memory controller a second read command and the second address; .
means for receiving from the main memory controller in response to sa~d second read command a first c~nnect data word and storing said ~rst connect data word;
means for receiving ~rom memory in response to said second read command, a second connect data word and storing said second connect data word;
means for testing the f~rst connect data word received to deter-mine if ~t is vali~d;
means f~r term~nat~ng th~ commun~cat~on i~ the said first connect data word is not valid; and means for ~ssuing the mai~n memory controller the wri~te remote reg~ster command, the $~rst connect data word, and the seccnd connec~ data word.
Accord~ng to another broad aspect o~ t~e inventi~on there ~g pro~
~ded, ~n a data proce5s-ing system hav~ng a data processor a main memory and a ma~n memory~controller;
sai~d data processor having a scratchpad memory7 a ~hiter, swi~tches~
arithmetic. and logic unit, adders and a plural~t~ of registexs including a data ~n register and an instructi~on regi~ster, sai~d instruct~on register responsi~e to t~e recelpt o a connect i~nstruct~on word from~a main memory : ~5~_ via a main memory controller ~ni~ti~ati~ng a mi~croprogram to accomplish the instruction; said m~croprogram compris~ng the steps of:
obtaining from the scratchpad memory of said processor a flrst address, said first address being the address of the base o~ a reserve memory segment of a main memory, s~or~ng said first address in a first temporary aase register, shifting a predetermined number of bit positions to the left, a first data word stored in the data in register of said processor, said data word designating a processor of said data processing system to be communicated with; and storing the first data word after belng 10 shifted in a first temporary reglster;
` generating a second address by adding a predetermined number to f t~e first address and issuing a ~irst read double command and the second ~: address to the main memory controller of the main memory;
shifting the first data word stored in said first temporar~ base register 29 bit positions to the right and storing said f~rst data word after being shifted in said first temporary register;
waiting until in response to the issuance of said first read ~` double command a second data word is stored in the data in regi~ster said second data word being the offset to the base address of the reser~e memory segment o~ a plurality of connect data words, adding to the second data word the data word stored in said ~Irst temporary register and storing the sum in a temporary address reglster; and receiving in the data in register ~n response to the first read double . command a third data word; said third data word being a write remote regis-ter communications command;
adding the contents of said first temporary~base register and said temporary address register to produce a third address, said third address be~ng the address in the reserve memory segment o~ the first o~' a palr of connect data words, said connect data words providing informati~on necessary ; 30 to cause the main memory contr~ller to communicate with the designated ' . ~
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processor; i~ssuing a second read double cammand and sa~d third address to the main memory controller o~ the main memory; storing the third data word, the write remote register command in a second temporary register;
waiting until the first connect data word is received by the data in register in response to said second read double command;
transferring the first connect data word to a third temporary register; receiving the second connect data word into the data in register in response to said second read douale command; and checking the first connect data word to determine if all bit positions are zeroes;
terminating the microprogram if all ~i~ positions of the first connect data word are zeroes;
and if all bit positions o~ the first connect data word are not zeroes;
issuing to the main memory controller the write remote regi~ster command, the first connect data word, the second word of connect data and terminating the microprogram.
rn ~ecordanee w~th another broad aspec* of t~e invention there is provided, in a data processing system ha~ing a data processor; said pro- :
cessor having a temporary base register, temporary registers, arithmetic logic units, temporary address registers, instruction register and a data in register said instruction register responsive to the receipt o$ a connect i~nstruetion from a main memory ~ia a main memory~ eontroller ~n~tiating a microprogram stored in an execution control store o~ the processor to cause predetermined data words to be communicated to a processor o said system, the processor to ~e communicated with being designated b~ a first data word stored in the data in register; the improvements comprising: ' means responsi~e to the first microinstruction of said mi~croprogram ~:
or obtaining from a scratchpad memory of said processor the address of the base of a reserve memory segment o a main memory and for storing said address in a temporary base register; means for shiting a predetermined ~, r5d-' ' `-" ~.gL6;;~6~
;` number of bit positions to the left the first data word stored in sald data in register; and for storing the data word aeter being shifted in a ~irs~
- temporary register;
means responsive to the second microi~nstruction o~ said micropro-gram for adding a predetermined numaer to the address of the base of the reserve memory segment stored in the temporary base register to produce a first address in the reserve memory segment of said main memory and for issuing a first read double command to the main memory controller of the main memory and said first address; the data words fetched from main memory in response to the first read double command being a second and a third data word, said second data word being the offset from the base address of a block of connect data words and the third data word be~ng a write remote register communication command; and means for shifting a predetermined nu~ber of bit positions to the right the ftrst data word stored in said fiTst temporary regi~ster and storing sa~d ~irst data word after being shifted in said first temporary regi~ster, means responsive to the third microinstruction of said micropro- :`
gram for storing in the data in regi~ster said second data word;
means responsive to the fourth m~croinstruct~on of sa~d micropro-~0 gram for adding to the second data word the data word stored in said first temporary register and storing the sum in a temporary address register and for storing the third data word in the data in register, means responsive to the fi~th microi`nstruction of the micropro-gram for adding the contents of the temporary address regis*er and said temporary base register to produce a second address in the reserve memory segment, said second address being that o~ the first o~ a pair of connect ~ -data words, said connect data words providing in~ormation to the main memory controller to cause said controller to communicate with the designated processor; for issuing a second read double command to the main memoTy controller of the main memory and said second address, and for storing the -Se~
:'~
t~ird data word in a second t~mporary regist~r~
means responsive to the six~h microinstruction of said micropro-; gram for receiving in the data in register the firs~ word of connect data;
means responsive to the seventh microinstruction of sa~d micropro-gram or storing the first connect data word in a third temporary register, for storing the second connect data word in the data in register; and for checking the first connect data word to determine if all lts blt positions are zeroes;
means responsive to the eighth micro~nstruction of the micropro-gram for terminating the microprogram if all ~it positions of the first connect data word are zeroes; and if the test indicates that the ~irst connect data word ls not all zeroes, means responsive to a ninth, tenth, and eleventh microlnstruction for issuing to the main memory controller the write remote register command, the first word of connect data, the second word of connect data, and for terminating the microprogram.
The-above and other o~ects of the invention, together with features and advantages thereof will become apparent from the following detailed description of a preferred embodiment of the ~nvention when consid-ered in conjunction with the attached drawings.
I/RlE t ~ 1 P IO: (IF T 1: DII~ S
Pig. 1 is a block diagram of an improved mult~processor data processing system, the CPU's of which ~ncorporate my invention.
Fig. 2 is a flow chart of tTIe connect microprogram, - Fig. 3 is a block diagram of the components of a CPU which, in ; response to control signals derived from t~e ~croprogram, initiate communication with another processor of the system.
Fig. 4 is the format of a part o~ ~he reserve memory portion of a main memory of the computer system.
~ig. 5 is the format of instruction words and data words used in ~5~-: . ;
6Z6~
the data processing system o~ ~ig. 1.
~ig. 6 is the format o~ the microinstructions used ln the connect microprogram. -~
-~ Fig. 7 is the ~ormat of the control un~t control store data word.
Flg. 1 is a ~lock diagram o~ a maxlmum c~n~igurat~on wlth respect to processors of an improved da~a processing system 10 in which the present in~ention is incorporated. Data processing system 10 has two SIU's 12a and 12~. Each SIU 12 has 15 ports identi~ied ~y letters A through K plus four additional memory ports~ local memory-port 0, (LMa)~ local memory port 1, CLMl~ ~
. -`
-'' ~', .' ;, ,.:
;' ' -5,g~
~ ,.
and two main memory ports in which the main memory control function or con-trollers (MMCo) and ~MMC1) are located. On certain pairs of ports such as G and H and ports E and F, a pair of locked I/O processors (IOP/P) 14a, 14b, 14c 14d can b~ attached.
OS Up to four central processing units (CPUs) 16a, 16b, 16c and 16d, two to each SIU can be attached to any two of ports A, B, C, D, E, F, G, or H of each SIU. Local memories (LMo) 18a, 18c or (LM1) 18b, 18d can be connected to local memory ports (LMo) 20a, 20c and (LM1) 20b, 20d of each SIU 12 and a main memory (MMo) 22a, 22c and (MM1) 22b, 22d can be connected to the main mernory controller MMCo 24a, 24c and MMC1 24b, 24d of the SIU's 12a and 12b. Each of the main memory controllers MMCo 24a, 24c or MMC1 24b, 24d of the SIU's 12a, 12b has two ports and each of the main ; memories 20a and 20b also has two ports which are cross-connected to permit communication to occur between devices and memories , attached to the respective SIU's 12.
Each of the main memory controllers MMCo 24a, 24c, MMC
24b, 24d of SIUs 12a, 12b in addition to writing data into a main memcry MMo 221, 22c, or MM1 22b, 22d and to reading data out of an MMo or MM1, also has certain communication control functions.
Communications between SIU's can be from a main memory controller such as MMCo 24a of SIU 12a to the main memory MMo 22c of SIU 12b. MMo 22c communicates or transmit the message to its main memor~ controller MMCo 24c of SIU 12b. MMCo 24c in turn directs the communication to the designated port of SIU 12b to which is attached a processor such as IOP/P 14c or CPU 16c, for example, of SIU 12b the processor to which the communication is directed.
' - ~ . .;; : - :: , A CPU such as 16a in the course of performing an application program, ~ill reach a point where an I/O operation is required either to bring in From d peripheral device data stored on the peripheral device or to read out from memory 05 information to be -transferred to a peripheral deYice. When the need for an I/O operation occurs, or more broadly~ whenever one processor needs to communicate with another processor including itself, the operating system of data processing system 10 will cause an instruction to be transm;tted to a CPU such as 16a for example. The contents of the operational field of the instruction word is such as to indicate or designate that a specific type of communication is to be performed or executed. The operating system will also provide 16a a data word~ a certain designated field of ~hich will identify the processor to which the ` 15 communication is to be sent. The details of the apparatus and i method to do this will be more fully~described later.
The field identifying the processor is a three bit field located in the lowest order positions of the operand, or data word. Fig. 5B illustrates the format of such a data word with the field identifying the processor occupyîng bit positions 33-35.
It can be seen3 however, from Fig. 1 that it is possible to connect up to four processors to each of two SIU's 12a, 12b which processors can be connected to various ports so that the necessary information needed to uniquely identify CPU 16b or IOP/P
14d, for example, to which the communication is to be sent canno~
be adequately specified by a three bit field. Thus, additional information is required. The additional information required is stored in a reserve memory portion of main memory such as MMo 22a of SIU 12a. The reserve memory portion illustrated in Fig. 4 of a main memory is a con~inguous block of memory~ whose position ~7-- : . ,; . . . ;. . .. .
in main memory 22a and the data words stored therein is established at the time data processing system 10 is initialized prior to beginning~?processing of application programs.
To perform the connect function, the processor has to 05 generate the addresses in the reserve memory to fetch the necessary information so that SIU 12a can steer the communication to the correct processor on the correct SIU 12 as well as -to provide that processor with the correct signals to cause it to initiate the desired function. In addition it is necessary for CPU 16a to retransmit or issue to the main memory controller MMCQ
24a of SIU 12a this information. Main memory controller MMCo 24a of SIU 12a then provides the necessary signals in the form of data words to be transmitted by SIU 12a to the addressed processor.
Main memory controller 24a will recognize the communication command and the data words transmitted to it as requesting special handling As a result, main memory controller 24a causes the necessary ~-communication signals and information to be transmitted to the desi~nated IOP/P or CPU either directly, if the designated processor is connected to the same SIU to which the main memory controller receiving the connect command is connected or, through a corresponding main memory 22c and main memory controller 24c of SIU 12b if the processor to be communicated with is attached to a port of SIU 12b. As a result of the information and signals transmitted to the designated processor, that processor knows that it is being requested to do something, and is provided with the necessary information requried by the designated processor to perform the desired function whether it is an I/O function, such as is typically provided by an IOP/P, or some other type of function which may be performed by a CPU.
~ ,, .. . . . . . .... . .
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Fig. 2 is a flow chart of the connect microprogram identifying each of the microinstructions of the microprogram that is executed by a CPU's execution unit in executing the connect microprogram. Fig. 3 is a block diagram of the hardware 05 elements of a CPU 16 which are utilized in the performance of the - connect microprogram. The connect instruction is received from an instruction buffer, which is not illustrated, over the instruckion buffer bus ZIS 26 from main memory controller such as MMC0 24a and is transmitted through ZI8 switch Z8 to RBIR 30 for storage therein. Fig. 5A is the format for an instruction word with the ten bit field, bit locations 18-279 being the operation code~
The operation code of an instruction word is the address in the control unit control store (CCS~ 32 of a control unit control word the format of which is illustrated in Fig. 7.
~ 15The control unit control store word stored in CCS 32 is `~ comprised of 32 bits. The thirteen bit field consisting of bit positions 0 through 12 is the address of the starting location for the microprogram specified by the operation code of the instruction stored in the instruction register RBIR 30 or the address of the initial microinstruction of the microprogram.
When the op code, from an instruction, is applied to the CCS 32 from RBIR 30, the control unit control word stored at the address corresponding to the op code, the contents of bit position 0 through 12 will be applied to the execution control store (ECS) -34 through switch CCS-ADR 36. The receipt of the address of a microinstruction by ECS 34 causes the microinstruction stored at that address to be transferred to the microinstruction control register 38 where selected fields of the microinstruction are decoded by decoder 40 to provide the necessary control signals or information to the various subsystems, or components, of a . .
~ '.
CPU such as CPU 16a, for example as will be more flIlly described later.
Referring to Fig. 2, the fIow chart of the connect microprogram, the contents of each block identifies the various 05 functions to be performed during a given clock period. Since processor 16a is a synchronous processor, all functions are synchronized by clock pulses as is well known in the art. To avoid providing unnecessary details, the clock and the conductors that apply the clock signals to the various components of CPU
16a are not illustrated in Fig. 3.
The operating system initiates the connect microprogram by issuing an instruction in which the operation code designates connect as the function to be performed and that code is the address o~ a 32 bit word stored in control unit control store 32.
The first 13 bits of that control word, the format of which is illustrated in Fig. 7, are applied to the execution unit control .
store ECS 34. The thirteen bits are the address of the first ~ -microinstruction of the microprogram, and as a result of there ; being applied to ECS 34, the first microinstruction of the ;~ designated microprogram is transferred to the microinstruction control register 38. `
Immediately after the operating system of data processing system 10 transmits a connect instruction to instruction register RBIR 30 of a CPU 16a, a 36 bit data word whose format is as illustrated ;n Fig. 5B is trans~erred from an operand buffer, which is not illustrated, to the data in register RDI 42 over data bus ZDI 43 through switch ZDI 44. When the first microinstruction 45 of connect has been loaded into the microinstruction control ~`
register 38, and durîng the next clock period, microinstruction 45 will be decoded in decoder 40 to provide the necessary ;
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information and con~rol signals to cause the scratchpad memory SPM 46 to be addressed and the con~ents of location 07 of SPM
46 to be transferred and stored in register T Base 0 48. This iâ accomplished by energi~ing or ~ating switch RSP 50 so that ~ 05 the signals stored in location 07 of SPM 46 are applied to data `- bus ZSP-DI 52 by energizing switch ZSP-DI 54 which applies the contents of location 07 of SPM 46 to data bus ZRESB, 56 and by energizing switch ZRESB 58 and register T Base 0 48. As a result, the data stored in the location 07 of scratchpad memory 46 is transferred and stored in register T Base 0 48. The ~` information stored in T Base 0 48 is the base address of the reserve memory portion 60 of main memory 22a, for example, which ,~ was stored in SPM 46 when data processing system 10 was initialized.
~ig. 4 illustrates the format of the reserve memory segment or portion 60 of main memory 22a, for example. During the execution of the first microinstruction 45, the data word3 or operand, of 36 bits, the format of which is illustrated in Fig.
5B, which was stored in the data in register RDI 42, immediately after the connect instruction word had been received by the instruction register RBIR 30, is read out of data in register RDI 42 through switch RDI 62 through shifter 64 which is `
energized and controlled by the microinstruction to shift to~the left by 33 places the informational content of the data word to eliminate any information that might have been placed in the higher order bit positions of the data word. It should be noted that the three bit field represented by bit positions 32 through 35 designate the processor with which the eommunication îs to be established. A preferred embodiment of shifter 64 embodiment is disclosed in application Serial No. 559,115 filed March 17, 1975 entitled Data Alignment Circuit and is assigned to the same - 1 1 - : :
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assignee~as this application, ~herefore, its details are not illustrated. The output of shifter 64 is stored in teMporary register TR 0 66, which is one of a bank of four such registers, by switch ZSHF 68 being eneryized by the microinstruction.
05 At the end of the first microinstruction 45, the base ~ address of the reserve memory segment has been stored in register T Base Q 48, and the three bit field of the data word stored in the data in register 42 which designates, or identifies, the processor to be communicated with, has been shifted to the left so that it occup;es the three highest order bit positions 0, 1 and 2 of the data word stored in register TR 0 66.
The next or second microinstruction 6~, which is produced as a result of the address of the first microinstruction which is stored in microinstruction register UIC 70 being incremen~ed lS by 1 by adder 72 and being applied through switch UIC+l, 74 ~;
wi71 cause the second microinstruction to be transferred to microinstruction control register 3$~ During the second clock period, the second microinstruction causes the data out register -`
RAD0 76 to have loaded into it a read double command and an ` 20 address.
The address is generated by the address preparation means illustrated in Fig. 3 which is comprised of carry save adder 78, carry save adder 80 and adder 82. The construction of adders 78, -80 and 82 is conventional and well known in the art and is, therefore, not illustrated in further detail. The ZX and ZY
- inputs to the adder circuit are specified in the microinstruction;
i.e., bit positions 55 through 57 and 58 through 60 of the ~ ~-microinstruction, see Fig. 6 for the format of a microinstruction.
In microinstruction 69 the ZX input is zero and the ZY is 04.
The output of the adder 82 which is applied to data bus ASFA 83, .:
which is the sum of the base address plus 04, is the address oF
f the first connect data word in the reserve memory segment which, as illustrated, is located at address location 4 of reserve memory portion 60.
05 Since a read clouble command was issued to the main memory controller, MMCo 24a of SIU 12a the word in location 5, which is the write remote register (WRRR~ communication command will also ~ be fetched as a result of the execution of second microinstruction `. 6g.
Dur;ng the execution of second microinstruction 69, while the address of the first of two words in the reserve section 60 are being generated and the read double command is being issued, the contents of TR 0 66, the three bit field, which now occupies the most significant bit positions; and which identify the : 15 processor to be communicated with, is again routed th~ough shifter 64 through switch RTR0-3B 84 and shifter 64 is con~rolled by microinstruction 69 to shift the data word applied to it to the right 29 positions which places the three bit field in proper alignment to be added to the base address of the block 86 of connect data words in the reserve memory segment 60 to provide the address of the first of a pair of connect data words associated with and required to communicate with the processor designated by the 3 bit field. The output of shi~ter 64 is then routed through switches ZSHF 68 so that it is again stored in TR 0 66.
During the third microinstruction 90, which is fetched from the execution unit control store 34 as a result of the address of ` .
the previous microinstruction being incremented by one and being : applied to ECS 34 through switch 74, the microprogram will wai~
until the first word is transferred from main memory, MMo ?2a of SIU 12a into the data in register RDI 42 through switch ZDI 44 .~ , .
~6~L, from data bus ~DI 43. This f;rst data word, read out oF memory in response to the read double command issued to the main memory controller during the execution of the second microinstruc~ion 69, is the contents of address location four in the reserve memory -- 05 section 60 and is the address of the base, or first data word, in block 86 of connect data words locations 50-67 in octal, in Fig. 4.
After the first data word has been read into the data in register RDI 42, the fourth microinstruction 92 will be fetched from the execution control store 34. The contents of RDI 42 are added to the information stored in TR 0 66 and are stored in register TEA-0 94. This is accomplished by having the contents of RDI and TR O applied to arithmetic and logic unit (ALU) 96 by energizing switch RDI 62 and switch RTRO^3A 98. The output of ALU 96 is stored in the temporary affective address register `:
TEA-O 94 bt energizing switch ZALU 100 and switch ZRESB 102.
The information stored in register TEA-0 is the sum of the offset of the first of the connect data words with respect to the base of the reserve memory portion 66, 50 in the example illustrated, ~` 20 plus an additional offset to provide the address which corresponds to the processor designated to be communicated with by the three bit field of the data word stored in the data in register RDI 42 at the time the connect microprogram began executing. During the .
execution of the fourth microinstruction 92, in response to the -.
read double command issued during microinstruction 69, the data ~ :
word from location five in the reserve memory portion 60 the ~ write remote register communications command WRRR Com CMD is read : into the data in register RDI 42 through switch ZDI 44. At the completion of the fourth microinstruction 92, the address in ~; 30 microinstruction register 70 is incremented by one by adder 72 and . ~
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and the address of the ~ifth microinstruction 104 is applied to the execution control store 34 and the fifth microinstnuction is then transferred from control store 34 to microinstruction control register 38.
05 During the clock period associated wTth the fifth microinstruction 104, the fifth microinstruction 104 causes a read double command to be loaded into the data out register RADO
76 and the address of the first of the two connect data words associated with the p,rocessor to be communicated with to be generated by the address generat;ng mechanism of CPU 16. The contents of register T Base O 48 and TEA-O 94 are applied through switches R Base T 106 and REA-T 108 to carry save adder 78 and 80 and adder 82 to produce the address of the first of the pair of connect data words that provide the necessary informatîon to a main memory controller for it to communicate with the designated processor. It can be seen from Fig. 4 that each pair of connect data words beginning with location 50 and ending with location 57 in octal are associated with a designated IOP/P 14 and that each pair of connect data words beginning with location 60 and ending with location 67 are associated with a designated CPU 16.
During fifth microinstruction 104, the contents of the data in register RDI 42 are transferred to and stored in TR 1 66. This is accomplished by energizing switch RDI 110, and switch ZSP-DI ' -~
112 to direct the signals for storage in one of a block of temporary storage registers 66, particularly TR 1. The da~a word stored in TR 1 66 is the WRRR communication command, the second data word read out of the reserve memory segment 60 in response to the : read double command ;ssued under the control of the second microinstruction 69.
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The sixth microinstruction 114, which is the result of incrementing the microinstruction stored in register 70 by one, causes the processor 1~a to wait until the first word is received from the main memory controller MMCo 24a of main memory 22a of 05 SIU 12a and is stored in data ;n register 42. When the first connect data word WRRR is received in RDI 427 the microinstruction - address stored in register 70 is incremented by one and the seventh microinstruction 116 is transferred to the microinstruction control register 38. The seventh microinstruction causes the first connect data wGrd to be transferred from RDI 42 for s~orage in temporary register TR 2 66 via the arithmetic and logic unit 96. This is accomplished by energizing switch RDI 118 and switch - ZALU 120, which causes the first connect data word to be routed to TR 2. During the seventh microinstruction, the second connect data word, in response to the issuance of a read double command during the fifth microinstruction 1043 is transferred from main memory 22a through the main memory controller MMCo 24a tG the data in register RDI 42. Also during the seventh microinstruction 116, the first connect data word, as pointed out above, is `~-transmitted through ALU 96 so that its contents can be checked to see if all of the bits in the first connect data word are zeroes. If all bit positions are logical zeroes, test block 122 will produce a logical one signal. The output of test block 122 is gated through switch ZALUZ=1 124 to go flip flop 126 which is set. Flip flop 126, when set, disables switch 74 and enables switch 128. In initializing the data processing system 10 the presence of logical zeroes in all bit positions of the firstl ~ -connect data word denotes, or represents, that there is no corresponding processor attached to the system.
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The address of microinstruction 116 stored in register 70 is incremented by one and the eighth microinstruction 130 is transferred to the microinstruction control register 34. During the execution of the eighth microinstruction, the contents of TR 1, 05 which is one of a group of register 66, ;s transferred to the data out register RAD0 76. This is accomplished by energizing switch RTR0-3A 98 which causes the signals from TR 1 to pass through ALU 96 and by the energizing switch ZALU 100 which will put the contents of TR 1 on data bus ZRESB 56. Energizing switch ZRESB 134 causes the contents of TR 1 to be loaded into register RAD0 76. The contents of TR 1 is the write ~emote register communication command, WRRR, which was fetched from memory and received during microinstruction four.
If the test of the contents of the first WRRR data word discloses that all bit positions were logical zeroes, and, `~ therefore, there was no processor connected to data processing system 10 corresponding to that three bit code or port number, then go flip flop 126 will be set and the switch UIC+1, 74 will be disabled. The branch address switch ECS-BR ADR 128 will be energized. Microinstruction 138 is then applied to control register 38 and signifies that the processor to be communicated with is nonexistent, or to state it another way, that an illegal port number has been utilized, or an illegal procedure fault has occurred, and the connect microprogram is terminated. (IPR fault occurs.) If the result of the test is negative, then go flip flop 98 does not change state, the microinstruction in register 70 is incremented by one so that the ninth microinstruction 136 will be applied to the control register 38. The ninth microinstruction 136 causes the contents of RAD0 76 to be issued to the memory controller MMCo 24a of SIU 12a.
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.
The tenth microinstruction 140 is produced at the next clock pulse as a result of the address of the ninth microinstruction in register 70 being incremented by one and being applied to the execution control store 32 through switch 74. The tenth 05 microinstruction causes the contents of TR 2 to be transferred to the RAD0 76, the routing being the same as that which caused the ! WRRR command to be transferred from TR 1 to RAD0 76. The data word stored in the data out register RAD0 76 is the first connect data word that was read out of the reserve portion 60 of main memory 22a, and which was received ~uring the sixth microinstruction 114. This word is also issued to the MMCo 2~a of SIU 12a. The microinstruction in register 70 is incremented by one and tbe address o~ the eleventh microinstruction 142 is applied to the ECS 34. The eleventh microinstruction is applied to control register 38 and causes the contents of RDI 42 to be transferred to RAD0 76. This is accomplished by energizing switch RDI 110, '.
switch ZSP-DI 54 which connects the contents of register RDIl42 onto data bus ZRESB which is then switched into RAD0 7~ through switch ZRESB 134. This is the second word of connect data which is then issued to MMCo 24a of SIU 12a. The eleventh microinstruction being the last microinstruction of the connect microprogram also causes the connect microprogram to terminate.
The format of the microins~ruct;on for CPU 60, particularly the fields relevant to the connect instruction, is illustrated in Fig. 6. The field EUFMT (2:1) defines the format of the ;
microinstruction from bit 0 through bit 31. For all microinstructions of the connect microprogram EUFMT is a logical 1.
.
`, The ~ield TR for Temporary Register write control (3:3) ' controls or determines into which of four rec~isters constitutin~
! a bank of re~isters identified as TR 66 a data word is to be ', temporarily stored. The following table determines the TR
registers into which a data word is to be s-torqd:
i O.YX No change .~ lOO Write TR-O
, - lOl Write TR-l .l llO Write TR-2 I~) 1].1 Write TR-3 The Z0PA field (9:4~ selects the output of the Z0PA
switches to be applied to the Z0PA data bus 144. The following table shows the relationship between the contents of the Z0PA
~ field and the outputs of the Z0PA data bus 144 that are relevant j 15 - to the connect instruction:
. ~) 0000 TR-O
', 1) OOO1 TR-l . ~
2) OOlO TR-2 ~ 3) OOll TR-3 i 2n 8-11) lOXX RDI
, 15) 1111 O (disable) ~ The Z0PB field (13:4) selects the output of the Z0PB
,j switches to be applied to the Z0PB data bus~146. The following I table sets forth the relationships between the conte.nts of the .~ 25 Z~P~ field and the source of the signals on the Z0PB data bus 146:
i O) OOOO TR-O
s~ 1) OOOl. TR-l ' ~ 2) OOlO TR-2 ~ 3) OOll TR-3 ¦ 31! 8-11) lOXX ~ RDI
~ 15) 1111 O (disable) ! -19-The ~ield %RESA (17:2) selects the output of the ZRES~
switches to be appl.ied to the ZRESA data bus 148. The following table sets forth the relationship between the contents of the %RESA field and the source of the signals on ZRESA data bus 148:
01 Shifter 10 Scratchpad/RDI switch I The field ZRESB (19:2) selects the output of the ZRESB
I switches to be applied to the ZRESB data bu~ 56. The following table sets forth the relationship between the contents of the I ZRESB fielcl and the source of the signals on the ZRESB data bus ~ 56:
¦ 00 ALU
~ 01 Shifter
3 15 . 10 Scratchpad/RDI switch j The field ZSPDI (23:1) selects the output of the scratchpad memory 46 or the output of data ln register RDI 42 which is to be applied to data bus ZSP-DI 52. The following table sets forth the relationship between the contents of the ZSP-DI field and 2n the source of the signals on the ZSP-DI data bus:52:
0 Scratchpad output : 1 RDI
`; The field ZSHF0P (24:2) lS the shifter operand shift control. It selects the operand to be applied -to the shifter ~4. The following table sets forth the relationship between the : contents of field ZSHF0P and the data bus over which the signals to be shifted are applied to shifter 64:
, 10 0 : : :
~ -20-i `
'I
i The field designated ALU (24:4) is the ALU function I control. This field selects the operation applied to the two i inputs (A and B) of ALU g6. The following table sets forth the relationship between the contents of the ALU ield and the operation performed by ALU 96 on the applied data words used in the connect microprogram:
1 1000 A+B (binary) ! The field ZALU (30:2) select3 the signals which are ~- 10 applied to data bus ZALU 150. In the connect microprogram only the following value for the ZALU field is used:
: i 00 AI,U output ¦ The CCM field (32:4) is used to provide a constant ¦ referred to by other fields of a microinstruction.
The field SELFLD (38:3), DRW (41:l) and TDRADR select a certain register and the data to be stored in~it. These fields are used when data is written into registers T Base 0 48 and register TEA-0 94 from data bus ZRESB 56. In the connect `~`
. microprogram, onlv the ~following values for the fields are used:
SELPLD DRW TDRaDR
¦ 0100 0 00 T Base 0 ~s 0101 0 00 ~ TE~-0 The SRAD0 field (52:2) is the RADO register strobe. It causes the RADO register to be strobed with selected data. The `¦ - 25 following table provides the functions that occur for the various ¦ combinations of signals in this field:
'I 00 NO strobes I 01 Instruction address into kADO
`¦ 10 Data to RADO
1 30 ll Operand address into RADO
;l , :
The TDR0 field (54:1) in con~unction with the TDRl field i (66:1) selests the TDR readout. In the connect microprogram only j the following values for these field are used:
1 1 which connects the output of TEA-0 82 to data bus ZZ 152.
The ZX field (55:3) selects the output which is applied to the ZX data bus 154. In the connect microprogram only the following values are used:
110 The ZY field (58:3) selects the output which is applied ! to the ZY data bus 154. In the connect microprogram only the .~ following values are used:
~ 011 which connects the signals stored in field CCM
;~` 15 (32:4) to the ZY data bus 156.
~¦ The field MEM (68:4~ selects the memory operation to be ~ performed in con~unctlon with field SZ (72:2). The following j table lists the values of the two fields used in the connect `¦ microprogram:
j20 MEM SZ
1 1010 01 Read double, Even-Odd `¦ 1111 XX Write remote l The IC field (71:3) controls the instruction counter `~ i register. It selects the operations to be performed on the RIC
¦25 register:
¦ 000 No operation I 001 End of mlcroprogram ~, . .
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The field FMT (87:1) determines the format of each ¦ microinstruction subsequent to bit 32. A11 microinstructions in the connect microprogr~l have the same format and this field in all these instructions is a logical 1.
,' 5 The field SPA (91:7) contains the address of a location ¦ in the scratchpad memory 46.
Field BRADRU (100:7) is the upper portion of a branch address. It contains the upper 7 bits of the address of a microinstruction located in ECS 34. Field BRADRL (107:6) is the Il 10 lower portion of a branch address. It contains the lower 6 bits ¦ of the address of a microinstruction in ECS 34. Together these ;, two fields provide the address in the ECS to which a microprogram ¦ jumps.
;~, Field EXIT terminates a microprogram when its value is ` I 15 one.
- The field INDGRP (119:5) is the conditional branch indicator group control. The first two bits, bit positions 119 and~ 120, select the group of microprogram indicators, and the ¦ last three bits, bit positions 121-123, select the "set" of ¦ 20 indicators within each group. In the connect microprogram the .
only values used in field INDGRP is: , 10 100 which denotes the indicators in Group l 2 set 4.
¦ Field INDMSU (1~5:4) contains the upper four bits of the conditional branch indicator mask. Field INDMSKL (129:4) - contains the lower four bits of the conditional branch indicator i' mask.
The shift count field (138:6) determines the number of ¦ positions a data word is shifted by shifter 64.
I
Fig. 5C is the format of the write remote register ' communication command WRRR. It is issued to a memory controller ¦ 24 during the execution of the connect microprogram. The field i FMT, bit position (0:1) determines the type of command. A zero ¦ 5 in bit position zero denotes that the command is a memory command ¦ and is recognized as such by a main memory controller 24. Thecon~and field (1:4) identifies the type of command to be executed ~¦ by the main memory controller. The zone field (5:5) is not used, i nor is the address field ~ 26) used in the write remote register communications command. In a preferred embodiment the command field for the write remote register command is 1110.
~ The first of the two write remote register data words ¦ format is illustrated in Fig. 5D. A logical 1 in bit positionI three is the only logical 1 in the first write remote register `~ 15 data word. It is transmitted to an SIU 12 unchanged. If there is il no processor corresponding to the number provlded in the data¦ word illustrated in Fig. 5D, then all of the bit positions of ¦ the first write remote register first data word will be zeroes.
Fig. 5E is the format of the second write remote register ¦~ 20 data word. The field PRO (0:1) determines whether the .
communication is with an IOP/P or a CPU. A logical zero designates that the communication is with an IOP/P and a loyical 1 that the communication is with a CPU. The field SIU (1:1) determines which of the two SIU;s the processor to be communicated - with is attached. The RFU field (2:2) is reserved for future use and, thus, is not used. The field SIU-P (4:4j identifies the port of the designated SIU to which the message is to be communicated.
- -2~-In a data processing sys~em 10 the communication ~unctions and operations are specified by the two WRRR data words associated with the WRRR/CQM~ command. Depending on the command, the two data words contain the specific communic~tion function to be relayed, the destination SIU
and port number and the mechanism to be used to signal the presence of the communication at the destination port.
I~hen the main memory controller MMC such as MMC 24a first receives the ~RRR command from SIU 12a, MMC 24a enters the WRRR/COMM
command into its command stack like any other memory command. Based on the contents of bit 1 in the second data word, the two WRRR data words are transmitted over one of two possible data paths to the designated processor.
Referring to Fig. 3, the various elements illustra~ed in the block i diagram of the CPU 16 can be fabricated from standard commercially available parts with the exception of shifter 64 which is described and claimed in U.S. patent No. 3,967,101 issued June 29, 1976 and assigned to the same assignee as the instant application. The registers, such as RDI 42, temporary register 66, for example, could be fabricated from semiconductor devices such as SN10130s which are standard commercial parts available ~0 from Texas Instruments. The switches, such as ZSHF 88, ZALU 120 for example, could be fabricated from semiconductor device such as an MC10174 which is available from Motorola. The ALU 96, the carry save adders 78, 80 and the adder 82 could be fabricated from semiconductor devices such as a Signetics 10181. The decoder 40 could be fabricated from semiconductor devices such as SN10161A which is available from Texas Instruments, and the scratchpad ``
memory 46 could be fabricated from parts such as SN10144 from Texas 'I
l, ¦ Instruments. ~he Texas Instruments parts are described in a - ¦ book entitled "ECL Series SN10000 for Desiyn Engineers" by Texas Instruments Incorporated, Copyright 1974. The Motorola part is described in a book entitled "MECL Integrated Circuits ~ 5 Data Book, Third Edition", Copyright 1973 by Motorola Incorporated.
¦ The Signetics parts are identified in a Signetics book entitled j "Signetics Digital, Linear, MOS, Data Book" published by the ! I Signetics Corporation Copyright 1974.
A review of Fig. 6 will show that most of the fields of ' 10 - the microinstructions used in the connect microprogram are coded `l ~ so they have to be decoded to produce the appropriate signals to ! - control ~he various switches, registers, arithmetic and logic ¦ units, etc., to produce the desired results. All such functions and capabilities are well known to those skilled in the art and, therefore, have not been illustrated in detail for the purpose I of simplifying the specification. The book "Microprogramming I Principles and Practices" by Samir S. Hasson, published by `¦ Prentice Hall, sets ~orth the principles of microprogramming as I of its copyright date of 1970 as is relied upon as showing the -¦ 20 state of the art as of that tlme.
From the foregoing explanation, it will be seen that the .
Applicant has provided a simple and economical solution to the problem of communicating data from one processor to another in a multiprocessor data processing system which is co~patible with a prior system.
¦ It should be evident that various modifications can be made to the described embodiments without departing from the I scope of the present invention.
What is claimed is:
0 Scratchpad output : 1 RDI
`; The field ZSHF0P (24:2) lS the shifter operand shift control. It selects the operand to be applied -to the shifter ~4. The following table sets forth the relationship between the : contents of field ZSHF0P and the data bus over which the signals to be shifted are applied to shifter 64:
, 10 0 : : :
~ -20-i `
'I
i The field designated ALU (24:4) is the ALU function I control. This field selects the operation applied to the two i inputs (A and B) of ALU g6. The following table sets forth the relationship between the contents of the ALU ield and the operation performed by ALU 96 on the applied data words used in the connect microprogram:
1 1000 A+B (binary) ! The field ZALU (30:2) select3 the signals which are ~- 10 applied to data bus ZALU 150. In the connect microprogram only the following value for the ZALU field is used:
: i 00 AI,U output ¦ The CCM field (32:4) is used to provide a constant ¦ referred to by other fields of a microinstruction.
The field SELFLD (38:3), DRW (41:l) and TDRADR select a certain register and the data to be stored in~it. These fields are used when data is written into registers T Base 0 48 and register TEA-0 94 from data bus ZRESB 56. In the connect `~`
. microprogram, onlv the ~following values for the fields are used:
SELPLD DRW TDRaDR
¦ 0100 0 00 T Base 0 ~s 0101 0 00 ~ TE~-0 The SRAD0 field (52:2) is the RADO register strobe. It causes the RADO register to be strobed with selected data. The `¦ - 25 following table provides the functions that occur for the various ¦ combinations of signals in this field:
'I 00 NO strobes I 01 Instruction address into kADO
`¦ 10 Data to RADO
1 30 ll Operand address into RADO
;l , :
The TDR0 field (54:1) in con~unction with the TDRl field i (66:1) selests the TDR readout. In the connect microprogram only j the following values for these field are used:
1 1 which connects the output of TEA-0 82 to data bus ZZ 152.
The ZX field (55:3) selects the output which is applied to the ZX data bus 154. In the connect microprogram only the following values are used:
110 The ZY field (58:3) selects the output which is applied ! to the ZY data bus 154. In the connect microprogram only the .~ following values are used:
~ 011 which connects the signals stored in field CCM
;~` 15 (32:4) to the ZY data bus 156.
~¦ The field MEM (68:4~ selects the memory operation to be ~ performed in con~unctlon with field SZ (72:2). The following j table lists the values of the two fields used in the connect `¦ microprogram:
j20 MEM SZ
1 1010 01 Read double, Even-Odd `¦ 1111 XX Write remote l The IC field (71:3) controls the instruction counter `~ i register. It selects the operations to be performed on the RIC
¦25 register:
¦ 000 No operation I 001 End of mlcroprogram ~, . .
~, .`1 .
:l -22-`I `
The field FMT (87:1) determines the format of each ¦ microinstruction subsequent to bit 32. A11 microinstructions in the connect microprogr~l have the same format and this field in all these instructions is a logical 1.
,' 5 The field SPA (91:7) contains the address of a location ¦ in the scratchpad memory 46.
Field BRADRU (100:7) is the upper portion of a branch address. It contains the upper 7 bits of the address of a microinstruction located in ECS 34. Field BRADRL (107:6) is the Il 10 lower portion of a branch address. It contains the lower 6 bits ¦ of the address of a microinstruction in ECS 34. Together these ;, two fields provide the address in the ECS to which a microprogram ¦ jumps.
;~, Field EXIT terminates a microprogram when its value is ` I 15 one.
- The field INDGRP (119:5) is the conditional branch indicator group control. The first two bits, bit positions 119 and~ 120, select the group of microprogram indicators, and the ¦ last three bits, bit positions 121-123, select the "set" of ¦ 20 indicators within each group. In the connect microprogram the .
only values used in field INDGRP is: , 10 100 which denotes the indicators in Group l 2 set 4.
¦ Field INDMSU (1~5:4) contains the upper four bits of the conditional branch indicator mask. Field INDMSKL (129:4) - contains the lower four bits of the conditional branch indicator i' mask.
The shift count field (138:6) determines the number of ¦ positions a data word is shifted by shifter 64.
I
Fig. 5C is the format of the write remote register ' communication command WRRR. It is issued to a memory controller ¦ 24 during the execution of the connect microprogram. The field i FMT, bit position (0:1) determines the type of command. A zero ¦ 5 in bit position zero denotes that the command is a memory command ¦ and is recognized as such by a main memory controller 24. Thecon~and field (1:4) identifies the type of command to be executed ~¦ by the main memory controller. The zone field (5:5) is not used, i nor is the address field ~ 26) used in the write remote register communications command. In a preferred embodiment the command field for the write remote register command is 1110.
~ The first of the two write remote register data words ¦ format is illustrated in Fig. 5D. A logical 1 in bit positionI three is the only logical 1 in the first write remote register `~ 15 data word. It is transmitted to an SIU 12 unchanged. If there is il no processor corresponding to the number provlded in the data¦ word illustrated in Fig. 5D, then all of the bit positions of ¦ the first write remote register first data word will be zeroes.
Fig. 5E is the format of the second write remote register ¦~ 20 data word. The field PRO (0:1) determines whether the .
communication is with an IOP/P or a CPU. A logical zero designates that the communication is with an IOP/P and a loyical 1 that the communication is with a CPU. The field SIU (1:1) determines which of the two SIU;s the processor to be communicated - with is attached. The RFU field (2:2) is reserved for future use and, thus, is not used. The field SIU-P (4:4j identifies the port of the designated SIU to which the message is to be communicated.
- -2~-In a data processing sys~em 10 the communication ~unctions and operations are specified by the two WRRR data words associated with the WRRR/CQM~ command. Depending on the command, the two data words contain the specific communic~tion function to be relayed, the destination SIU
and port number and the mechanism to be used to signal the presence of the communication at the destination port.
I~hen the main memory controller MMC such as MMC 24a first receives the ~RRR command from SIU 12a, MMC 24a enters the WRRR/COMM
command into its command stack like any other memory command. Based on the contents of bit 1 in the second data word, the two WRRR data words are transmitted over one of two possible data paths to the designated processor.
Referring to Fig. 3, the various elements illustra~ed in the block i diagram of the CPU 16 can be fabricated from standard commercially available parts with the exception of shifter 64 which is described and claimed in U.S. patent No. 3,967,101 issued June 29, 1976 and assigned to the same assignee as the instant application. The registers, such as RDI 42, temporary register 66, for example, could be fabricated from semiconductor devices such as SN10130s which are standard commercial parts available ~0 from Texas Instruments. The switches, such as ZSHF 88, ZALU 120 for example, could be fabricated from semiconductor device such as an MC10174 which is available from Motorola. The ALU 96, the carry save adders 78, 80 and the adder 82 could be fabricated from semiconductor devices such as a Signetics 10181. The decoder 40 could be fabricated from semiconductor devices such as SN10161A which is available from Texas Instruments, and the scratchpad ``
memory 46 could be fabricated from parts such as SN10144 from Texas 'I
l, ¦ Instruments. ~he Texas Instruments parts are described in a - ¦ book entitled "ECL Series SN10000 for Desiyn Engineers" by Texas Instruments Incorporated, Copyright 1974. The Motorola part is described in a book entitled "MECL Integrated Circuits ~ 5 Data Book, Third Edition", Copyright 1973 by Motorola Incorporated.
¦ The Signetics parts are identified in a Signetics book entitled j "Signetics Digital, Linear, MOS, Data Book" published by the ! I Signetics Corporation Copyright 1974.
A review of Fig. 6 will show that most of the fields of ' 10 - the microinstructions used in the connect microprogram are coded `l ~ so they have to be decoded to produce the appropriate signals to ! - control ~he various switches, registers, arithmetic and logic ¦ units, etc., to produce the desired results. All such functions and capabilities are well known to those skilled in the art and, therefore, have not been illustrated in detail for the purpose I of simplifying the specification. The book "Microprogramming I Principles and Practices" by Samir S. Hasson, published by `¦ Prentice Hall, sets ~orth the principles of microprogramming as I of its copyright date of 1970 as is relied upon as showing the -¦ 20 state of the art as of that tlme.
From the foregoing explanation, it will be seen that the .
Applicant has provided a simple and economical solution to the problem of communicating data from one processor to another in a multiprocessor data processing system which is co~patible with a prior system.
¦ It should be evident that various modifications can be made to the described embodiments without departing from the I scope of the present invention.
What is claimed is:
Claims (7)
- Claim 1. The method by which a first data processor communicates with another data processor in a multiprocessor data processing system in response to the first data processor receiving from a main memory controller of a main memory having a reserve memory segment in which data words are stored in the system, an instruction word directing such a communication, and a first data word identifying the processor to be communicated with comprising the steps of:
fetching from a memory the base address of the reserve memory segment of the main memory;
adding to said base address of the reserve memory segment a first offset to produce a first address, issuing to the main memory controller a first read command and said first address;
receiving from the main memory controller in response to said first read command, a second data word, said second data word being a second offset from the base address of the reserve memory segment;
receiving from the main memory controller a third data word in response to said first read command said third data word being a write remote register command;
adding to the base address of the reserve memory, the second offset and the identification of the processor to be communicated with from said first data word to produce a second address in the reserve memory segment at which address the first of two connect data words needed to complete the communication with the processor to be communicated with are stored;
issuing to the main memory controller a second read double command and the second address;
receiving from memory in response to said second read command a first connect data word;
testing to see if the first connect data word is valid;
terminating the method if the said first data word is not valid; or transmitting to the main memory controller, the write remote register command, the first connect data word, and the second connect data word; and terminating the method. - Claim 2. The method by which a first data processor communicates with another data processor in a data processing system having a plurality of data processors and at least one main memory and at least one main memory controller, said main memory having a reserve memory segment in which data words are stored said first data processor in response to receiving an instruction word directing such a communication and a first data word identifying the processor to be communicated with, comprising the steps of:
fetching from a scratchpad memory of said first data processor the base address of a reserve memory segment of the main memory;
adding to said base address a first offset to produce a first address;
issuing to the main memory controller a first read double command and said first address;
receiving from the main memory controller in response to said first read double command, a second data word, said second data word being a second offset from the base address of the reserve memory segment of the first of a block of write remote register data words;
receiving from the main memory controller the second data word in response to said first read double command, said second word being a write remote register command;
storing said command in storage means in said first processor;
adding to the base address of the reserve memory segment, the second offset plus the identification of the processor to be communicated with obtained from said first data word to produce a second address in the reserve memory segment at which address location the first of two write remote register data words needed to complete the communication with the processor to be communicated with are stored;
issuing to the main memory controller a second read double command and the second address;
receiving from memory in response to said second read double command a first write remote register data word;
storing said first write remote-register data word in storage means in said first data processor;
receiving from memory in response to said second read double command a second write remote register data word;
storing said second write remote register data word in storage means in said first data processor;
testing to see if the first write remote register data word is valid;
terminating the method if the said first write remote register data word is not valid;
transmitting to the main memory controller, the write remote register command, the first write remote register data word, and the second write remote register data word; and terminating the method. - Claim 3. Apparatus by which a first data processor communicates with another data processor in a multiprocessor data processing system in response to the first data processor receiving from a main memory controller of a main memory of the system an instruction word directing such a communication and a first data word identifying the processor to be communicated with, said main memory having a main memory segment in which data words are stored, comprising;
means for fetching from a memory, the base address of the reserve memory segment of the main memory;
means for adding to said base address a first offset to produce a first address;.
means for issuing to the main memory controller a first read command and said first address;
means for receiving from the main memory controller in response to said first read command a second data word, said second data word being a second offset from the base address of the reserve memory segment, and for storing said first data word;
means for receiving from the main memory controller a third data word in response to said first read command, said third data word being a write remote register command, and storing said second data word;
means for adding the base address of the reserve memory segment and the second offset from the base address of the reserve memory segment received in response to the first read command, and the identification of the processor to be communicated with from said first data word to produce a second address in the reserve memory segment, said address being the location in the reserve memory segment where the first of two connect data words needed by the main memory controller to complete the communication with the processor to be communicated with are stored;
means for issuing to the main memory controller a second read command and the second address;
means for receiving from the main memory controller in response to said second read command a first connect data word and storing said first connect data word;
means for receiving from memory in response to said second read command, a second connect data word and storing said second connect data word;
means for testing the first connect data word received to determine if it is valid;
means for terminating the communication if the said first connect data word is not valid; and means for issuing the main memory controller the write remote register command, the first connect data word, and the second connect data word. - Claim 4. Apparatus by which a first data processor communicates with another processor in a data processing system having a plurality of processors, at least one main memory and at least one main memory controller, said main memory having a reserve memory segment in which data words are stored; said first data processor communicating with another processor, in response to the first data processor receiving from a main memory controller of a main memory of the system an instruction word directing such a communication and a first data word identifying the processor to be communicated with, comprising;
means for fetching from a scratchpad memory of said first data processor, the base address of the reserve memory segment of the main memory;
means for adding to said base address a predetermined number to produce a first address;
means for issuing to the main memory controller a first read double command and said first address;
means for receiving from the main memory controller in response to said first read double command a second data word, said second data word being a second offset from the base address of the reserve memory segment and storing said first data word;
means for receiving from the main memory controller a third data word in response to said first read double command said third data word being a write remote register command and storing said second data word;
means for adding the base address of the reserve memory segment and the second offset from the base address of the reserve memory segment received in response to the first read double command, and the identification of the processor to be communicated with from said first data word to produce a second address in the reserve memory segment, said second address being the location in the reserve memory segment where the first of two write remote register data words needed by the reserve memory controller to complete the communication with the processor to be communicated with are stored;
means for issuing to the main memory controller a second read double command and the second address;
means for receiving from main memory controller in response to said second read double command a first write remote register data word and storing said first write remote register data word;
means for receiving from memory in response to said second read double command, a second write remote register data word and storing said second connect data word;
means for testing the first remote register data word received to determined if it is valid;
means for terminating the communication if the said first connect data word is not valid; and means for issuing to the main memory controller the write remote register command, the first write remote data word, and the second write remote register data word. - Claim 5. In a data processing system having a data processor a main memory and a main memory controller;
said data processor having a scratchpad memory, a shifter, switches, arithmetic and logic unit, adders and a plurality of registers including a data in register and an instruction register, said instruction register responsive to the receipt of a connect instruction word from a main memory via a main memory controller initiating a microprogram to accomplish the instruction; said microprogram comprising the steps of:
obtaining from the scratchpad memory of said processor a first address, said first address being the address of the base of a reserve memory segment of a main memory, storing said first address in a first temporary base register, shifting a predetermined number of bit positions to the left, a first data word stored in the data inregisters of said processor, said data word designating a processor of said data processing system to be communicated with; and storing the first data word after being shifted in a first temporary register;
generating a second address by adding a predetermined number to the first address and issuing a first read double command and the second address to the main memory controller of the main memory; .`
shifting the first data word stored in said first temporary base register 29 bit positions to the right and storing said first-data word after being shifted in said first temporary register;
waiting until in response to the issuance of said first read double command a second data word is stored in the data in register said second data word being the offset to the base address of the reserve memory segment of a plurality of connect data words;
adding to the second data word the data word stored in said first temporary register and storing the sum in a temporary address register; and receiving in the data in register in response to the first read double command a third data word;
said third data word being a write remote register communications command, adding the contents of said first temporary base register and said temporary address register to produce a third address, said third address being the address in the reserve memory segment of the first of a pair of connect data words, said connect data words providing information necessary to cause the main memory controller to communicate with the designated processor; issuing a second read double command and said third address to the main memory controller of the main memory; storing the third data word, the write remote register command in a second temporary register;
waiting until the first connect data word is received by the data in register in response to said second read double command;
transferring the first connect data word to a third temporary register; receiving the second connect data word into the data in register in response to said second read double command; and checking the first connect data word to determine if all bit positions are zeroes;
terminating the microprogram if all bit positions of the first connect data word are zeroes;
and if all bit positions of the first connect data word are not zeroes;
issuing to the main memory controller the write remote register command, the first connect data word, the second word of connect data and terminating the microprogram. - Claim 6. In a data processing system having a data processor; said data processor having a temporary base register, temporary registers, arithmetic logic units, temporary address registers, instruction register and a data in register said instruction register responsive to the receipt of a connect instruction from a main memory via a main memory controller initiating a microprogram stored in an execution control store of the processor to cause predetermined data words to be communicated to a processor of said system, the processor to be communicated with being designated by a first data word stored in the data in register; the improvements comprising:
means responsive to the first microinstruction of said microprogram for obtaining from a scratchpad memory of said processor the address of the base of a reserve memory segment of a main memory and for storing said address in a temporary base register; means for shifting a predetermined number of bit positions to the left the first data word stored in said data in register; and for storing the data word after being shifted in a first temporary register;
means responsive to the second microinstruction of said microprogram for adding a predetermined number to the address of the base of the reserve memory segment stored in the temporary base register to produce a first address in the reserve memory segment of said-main memory and for issuing a first read double command to the main memory controller of the main memory and said first address; the data words fetched from main memory in response to the first read double command being a second and a third data word, said second data word being the offset from the base address of a block of connect data words and the third data word being a write remote register communication command; and means for shifting a predetermined number of bit positions to the right the first data word stored in said first temporary register and storing said first data word after being shifted in said first temporary register, means responsive to the third microinstruction of said microprogram for storing in the data in register said second data word;
means responsive to the fourth microinstruction of said microprogram for adding to the second data word the data word stored in said first temporary register and storing the sum in a temporary address register and for storing the third data word in the data in register, means responsive to the fifth microinstruction of the microprogram for adding the contents of the temporary address register and said temporary base register to produce a second address in the reserve memory segment, said second address being that of the first of a pair of connect data words, said connect data words providing information to the main memory controller to cause said controller to communicate with the designated processor; for issuing a second read double command to the main memory controller of the main memory and said second address, and for storing the third data word in a second temporary register, means responsive to the sixth microinstruction of said.
microprogram for receiving in the data in register the first word of connect data;
means responsive to the seventh microinstruction of said microprogram for storing the first connect data word in a third temporary register, for storing the second connect data word in the data in register; and for checking the first connect data word to determine if all its bit positions are zeroes;
means responsive to the eighth microinstruction of the microprogram for terminating the microprogram if all bit positions of the first connect data word are zeroes; and if the test indicates that the first connect data word is not all zeroes, means responsive to a ninth, tenth, and eleventh microinstruction for issuing to the main memory controller the write remote register command, the first word of connect data, the second word of connect data, and for terminating the microprogram. - Claim 7. A data processor comprising:
an instruction register adapted to receive instruction words from a main memory, said main memory having a main memory controller, predetermined bit positions of each instruction word constituting an operation code, a data in register adapted to receive data words from main memory, a control unit control store adapted to store control words, the operation codes of each instruction word being the address of a control word stored in the control unit control store;
an execution unit control store adapted to store microprograms, each microprogram comprising microinstructions, each control word of the control unit control store including the address in the execution unit control store of the first microinstruction of the corresponding microprogram;
said execution unit control store in response to an address being applied to it from a control unit control store, from a microinstruction register, or from a microinstruction in execution, causing the microinstructions stored at the address applied to the execution control store to be read into a microinstruction control register;
each microinstruction stored in said microinstruction control register controlling switches, shifters, arithmetic logic units, data out registers, data in registers and a scratchpad memory of the processor in accordance with the binary information of predetermined bit positions of each microinstruction;
said instruction register in response to the receipt of a connect instruction causing the control unit control store control word at the address corresponding to the operation code of said instruction to supply to the execution unit control store the address of the first microinstruction of the connect microprogram, said execution unit control store in response to such address, supplying to the microinstruction control register the first microinstruction of the connect microprogram, said first microinstruction stored in said microinstruction control register causing a data word to be fetched from the scratchpad memory from an address specified in the microinstruction, the data word fetched being the address of the base of a reserve memory portion of a main memory, said microinstruction causing said data word to be stored in a first register; causing a data word stored in the data in register, which data word contains information identifying the processor to be communicated with in performing the microprogram to be transferred through a shifter where it is shifted to the left 33 bits and the output of the shifter to be stored in a second register;
means for incrementing by one the microinstruction address in the microinstruction register and applying the new address to the execution unit control store, the receipt of the new address causing the second microistruction of the microprogram to be transferred to the microinstruction control register, said second microinstruction stored in said microinstruction control register causing the contents of the first register to be added to an amount specified in the microinstruction to produce a first address in the reserve memory portion of main memory; said first address being the address of a data word which contains the offset from the base of the reserve memory portion of a first of a set of data words containing the necessary information for communication with the designated processor; transferring the first address to the data out register together with a read double command and issuing said address and command to the main memory controller;-and causing the contents of the second register to pass through the shifter and to be shifted to the right 29 places, the output of the shifter being stored in the second register;
means for increasing by one the microinstruction address in the microinstruction register to transfer the third microinstruction to the microinstruction control register, said third microinstruction causing the processor to wait until the first word read out of main memory in response to the first read double command is stored in the data in register, this first data word being the offset form the reserve memory base of the location of the first of a set of connect data words associated with each possible processor to be communicated with;
means for increasing by one the microinstruction address in the microinstruction register to transfer the fourth microinstruction to the microinstruction control register, said fourth microinstruction causing the data word in the data in register to be added to the data word in the second register to produce a second address, said second address being the offset to the base address of the reserve memory of the first of the connect data words for the processor to be communicated with, and to store this second address in a third register; and causing the second data word read out of memory in response to the first read double command a write remote register command to be stored in the data in register;
means for increasing by one the microinstruction address in the microinstruction register to transfer the fifth microinstruction to the microinstruction control register, said fifth microinstruction causing the data out register to be loaded with a second read double command and a third address, said third address being formed by adding the contents of the third register and said first register to produce the address in the main memory of the first word of connect data for the processor to be communicated, and to issue a second read double command and the third address to the main memory controller; and causing the second data word read out of memory in response to the first read double command to be stored in a fourth register;
means for increasing by one the microinstruction address in the microinstruction register to transfer the sixth microinstruction to the microinstruction control register, said sixth microinstruction causing the processor to wait until the first word of connect data read out of main memory in response to the second read double command is stored in the data in register;
means for increasing by one the microinstruction address in the microinstruction register to transfer the seventh microinstruction to the microinstruction control register, said seventh microinstruction causing the first connect data word to be transferred from the data in register to a fifth register through the arithmetic and logic unit; causing a checking circuit to test the contents of the first connect data word to determine if it is all zeroes, and causing the data in register to store the second connect data word read out of main memory in response to the second read double command;
means for increasing by one the microinstruction address in the microinstruction counter to transfer the eighth microinstruction to the microinstruction control register, said eighth instruction causing the data word stored in the fourth register to be stored in the data out register and if the test of a first connect data word conducted during the eighth microinstruction indicates that the first connect data word is all zeroes, causing the address of the microinstruction to be applied to the execution control store to be a branch to an address, of a microinstruction representing that there is no processor to which the communication is to be sent and which terminates the connect microprogram; or if the test indicates that the contents of the first connect data word is not all zeroes, to transfer the contents of the fourth register the write remote register command to the data out register;
means for incrementing by one the microinstruction address in the microinstruction counter to transfer the ninth microinstruction to the microinstruction control register, said ninth microinstruction causing the data out register to issue to the main memory controller the write remote register command;
means for increasing by one the microinstruction address in the microinstruction register by one to transfer the tenth microinstruction to the microinstruction control register, said tenth microinstruction causing the content of the fifth register to be transferred to the data out register, and issued to the main memory controller;
means for increasing by one the microinstruction address in the microinstruction register to transfer the eleventh microinstruction to the microinstruction counter, said eleventh microinstruction causing the contents of the data in register to be transferred to the data out register and to issue the second connect data word to the main memory controller, and to cause the connect microprogram to terminate by branching to an exit location designated in the eleventh microinstruction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US74644476A | 1976-12-01 | 1976-12-01 | |
| US746,444 | 1991-08-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1116261A true CA1116261A (en) | 1982-01-12 |
Family
ID=25000860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA287,398A Expired CA1116261A (en) | 1976-12-01 | 1977-09-23 | Method and apparatus by which one processor in a multiprocessor computer system communicates with another |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5369564A (en) |
| AU (1) | AU3096277A (en) |
| CA (1) | CA1116261A (en) |
| DE (1) | DE2753621A1 (en) |
| FR (1) | FR2373101A1 (en) |
| GB (1) | GB1578205A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5833969B2 (en) * | 1978-07-26 | 1983-07-23 | 株式会社デンソー | Data transfer method |
| EP0408810B1 (en) * | 1989-07-20 | 1996-03-20 | Kabushiki Kaisha Toshiba | Multi processor computer system |
-
1977
- 1977-09-23 CA CA287,398A patent/CA1116261A/en not_active Expired
- 1977-11-25 AU AU30962/77A patent/AU3096277A/en active Pending
- 1977-11-30 FR FR7736195A patent/FR2373101A1/en active Granted
- 1977-12-01 JP JP14461377A patent/JPS5369564A/en active Pending
- 1977-12-01 DE DE19772753621 patent/DE2753621A1/en not_active Withdrawn
- 1977-12-01 GB GB5009577A patent/GB1578205A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2373101B3 (en) | 1980-09-05 |
| GB1578205A (en) | 1980-11-05 |
| FR2373101A1 (en) | 1978-06-30 |
| JPS5369564A (en) | 1978-06-21 |
| DE2753621A1 (en) | 1978-06-08 |
| AU3096277A (en) | 1979-05-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |