JPS63156263A - Maintenance system for adapter - Google Patents

Abstract

PURPOSE:To reduce the cost by not providing a dedicated interface but using an interface for data transfer provided between CPUs to perform the maintenance of an adapter. CONSTITUTION:Adapter control registers 21-24 which control scanning operation are provided in an adapter 2, and a CPU 1 accesses them. Data is read and written through the register 21 which forms a scanning loop together with FFs 25-30 in the adapter 2. A counter register 22 which designates the number of times of scan, a control register 23 which designates the start of scan, and a mode register 24 which designates the read/write selection mode are provided as registers, and they are controlled to set the adapter inside to a requested state, and the state is detected. Thus, the maintenance is performed without providing the dedicated interface to reduce the cost.

Description

[Detailed Description of the Invention] [Summary] The present invention is an adapter or channel dedicated to input/output transfer control that receives and receives startup instructions from a central processing unit (CPU) and exclusively controls data transfer to input/output devices. Regarding the maintenance method of the equipment called.

The present invention is a method for maintaining the adapter by using only the data transfer interface installed between the CPUs, without providing a dedicated maintenance interface.

This is a system in which maintenance of the adapter is performed by simply accessing a group of adapter control registers within the adapter from the CPU side.

In the present invention, all the flip-flops except the flip-flop that controls the scan operation inside the adapter are connected by a scan loop, and the CPU is connected in the scan loop.
A scan register is provided that can be accessed from the side to know the internal status of the adapter.

To control this scan operation, a scan counter that specifies the number of scans, a scan control register that controls the start of scans, and a selection mode such as read or write are selected from among the RAM inside the adapter. Set up a scan mode register to specify. Then, the CPU accesses the adapter control register group and learns the internal state of the adapter.

According to the present invention, there is no need to provide an interface dedicated to maintenance on the adapter, and the cost of the computer system can be reduced.

[Industrial application field]

The present invention relates to a maintenance method for an adapter that exclusively controls input/output transfer, and in particular, it does not provide a dedicated interface for maintenance, but effectively utilizes the data transfer bus connected between the CPU and the adapter to maintain the internal state of the adapter. This invention relates to an adapter maintenance method that makes it possible to know the status.

[Conventional technology]

A computer system is comprised of a central processing unit ffi (CPU) that decodes instructions and executes operations on data, a main memory that stores instructions and data, and an input/output device that processes input and output. Compared to the speed of the CPU, the input/output device is ta
The speed is slow because it involves TA operations, so in order to obtain high processing power of the computer system, a large number of input/output operations and CP are required.
Perform operations U in parallel. There are two methods for this purpose: an interrupt control method and a channel method. In the interrupt control method, the CPU directly controls input/output, but instead of waiting during input/output operations, an interrupt is generated and processed when a request is received from the input/output device side.

In the latter channel system, a device called a channel dedicated to input/output transfer control is provided, the CPU only activates the channel, and data transfer is performed directly with the main storage device under the control of the channel. This method uses an interrupt to notify the CPU from the channel only when the data transfer ends or when an abnormality occurs. This channel is also called an adapter, and standard ones have unified specifications regarding input and output interfaces. And to match that a 74'l, C
An extremely flexible interface is configured that absorbs the characteristics of the PU and allows any input/output device to be easily connected. In order to efficiently operate a plurality of connected input/output devices, a plurality of devices are connected to one adapter, and the devices are selected in a time-sharing manner.

A conventional system in which a plurality of adapters of this type are installed is shown in the block diagram of FIG. The CPUI and, for example, three adapters 2 are connected by a bus 3 consisting of 32-bit data and 32-bit addresses;
t5Aii is performed on the o, 8-bit, and g buses. Also, CPU
MSU4 is a storage device, and field maintenance device F is a device dedicated to maintenance.
In a conventional computer system of this type connected to the MD 5 by a bus 3 for data transfer, a data line 6 of an interface dedicated for maintenance is connected in a continuous manner in order to perform maintenance of the adapter. Adapter maintenance was performed using this maintenance-dedicated interface.

[Problem that the invention seeks to solve]

The conventional maintenance method for this type of adapter has the problem that the cost of the entire system increases because an interface dedicated to maintenance is provided.

[Means for resolving issues]

A configuration block diagram of a computer system according to the adapter maintenance method of the present invention is shown in FIG.

The present invention comprises a central processing unit (CPU) 1 that reads instructions and executes arithmetic processing, a field maintenance device 5 that executes maintenance control, a main storage unit (MSU) 4, and and an adapter 2 that exclusively executes control regarding input/output transfer and notifies at least the CPU of the end of the transfer. Each adapter 2 has a group of adapter control registers that control the scan operation, including a scan register that forms a scan loop with a storage means inside the adapter. Further, by accessing each register of the adapter control register group from the CPU, the state of the storage means inside the adapter connected to the scan loop is set to the requested state and operated, and the state of the storage means inside the adapter connected to the scan loop is set to the requested state and and control means for knowing the state via the scan register.

In this way, the present invention does not provide an interface dedicated to adapter maintenance, but has means for performing adapter maintenance by directly using the data transfer interface.

[For production]

The present invention provides a group of adapter control registers for controlling scan operations in each adapter, and enables access to the register group from the CPU side to read and write data via registers forming a scan loop with a flip-flop inside the adapter. Execute the following. The adapter control register group includes a scan counter that specifies the number of scans, a scan control register that specifies the start of scan, and a scan mode register that specifies modes such as read/write selection. By controlling the adapter, the inside of the adapter is set to the required state, and conversely, the state is known.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the internal configuration of each adapter and the overall system configuration according to the adapter maintenance method of the present invention.

In the system of the present invention, an adapter 2 is connected via a bus 3 to a central processing unit (CPU) 1 that decodes instructions and processes information, and a main memory 4 that stores instructions and data. This adapter is a device called a channel.
This is a device that exclusively performs control related to input/output transfer. Although not shown, an I10 device is connected to the adapter 2. Because input/output devices perform mechanical operations, their speed is slower than that of the CPU, so many input/output operations are performed by the CPU.
The adapter 2 controls the calculation so that it is performed in parallel with the calculation of U. The CPUI only activates input/output to the adapter 2, and transfers data related to input/output under the control of this adapter. In particular, the adapter 2 controls direct data transfer between the main storage device 4 and each input/output device, and only notifies the CPU by interrupting when the data transfer ends or when an abnormality occurs.

In such a system, maintenance of the adapter 2 is performed. Maintenance is necessary for the reliability and maintainability of the system, and it is necessary to minimize the occurrence of machine failures and to ensure that failures occur as soon as possible. It provides functions such as: In the present invention, the CPUI learns the internal state of the adapter 2 via the bus 3 with the help of the field maintenance device 5, and furthermore, the CPUI operates the contents of the RAM or registers inside the adapter in order to maintain the adapter 2. It is known under the control of the system (O3). The maintenance method of the adapter of the present invention differs from the conventional one in that the adapter 2 does not have a dedicated interface for maintenance.
This method uses only the bus 3 for data transfer of the adapter 2.

Inside each adapter 2 of the present invention, a scan register 21,
It has an adapter control register group consisting of a scan mode register 22, a scan control register 23, and a scan mode register 24. Further, the scan register 21 forms a scan loop with flip-flops 25, 26, 27, 28, 29, 30, etc. inside the adapter 2. The CPUI can access each register 21, 22, 23, 24 of the adapter control register group via the bus 3.

That is, arbitrary information of, for example, 8 bits can be set in each register, and at the same time, the CPU 1 can read 8-bit information from the scan register 21. C.P.U.I.
When the data is set in the scan register 21, the data is scanned on the scan loop 31. This causes the flip-flop 7 (25 to 3) inside the adapter 2 to
0) can be set to the required state. Also, the information of the internal combinational circuit or RAM is stolen into the flip-flop, and the scan data is passed through the scan loop 31 to the scan register 21. After that, when the CPU reads the ta information, the information is stored inside the adapter. You can know the status of

The scan counter register 22 sets the number of scans to be performed. The scan control register 23 is used to set information regarding the scan operation, and in particular, the scan is started by setting the internal start scan bit. The scan mode register 24 is a register for setting a scan mode such as reading and writing to internal RAM or selecting a plurality of RAMs, and has a configuration as shown in FIG.

The scan mode register consists of 8 bits.

The most significant bit, the LTM bit, is O, which means reading data from the internal RAM, and when it is 1, it means writing data from the RAM. The M bit to the next SC8 becomes 1 when scanning is performed. Ml to next R, 2. Bit 3 is used to select the target RAM from among multiple RAMs inside the adapter.
This is bit information.

The next 5 TART bits, if sent, will display RAM ALTER. The next 5SCAN bits are start scan bits, and when this bit is set, scanning is started.

Reading the register, that is, in the case of display mode, the M bit in SC8 of the scan mode register 24 is set to 1.0 Next, refer to the scan table in which the information of flip-flops 25 to 30 inside the adapter 2 is stored. Then, the scan count of the target register is set in the scan count register 22. After that, the S.C.A.
Scanning is started by setting NM focus to 1, setting the scan mode, and setting 5SCAN bit to 1. When the scan is completed, the scan register 21
The value you want to refer to is set.

By reading the contents of this scan register 21, the CPUI can know the internal state.

Next, the value of the register is rewritten, that is, the alternator (8 LTE
The case of R) mode will be explained.

As in the case of reading, first scan mode register 24
Set the SCANM bit of . Next, referring to the scan table, the scan count of the target register is set in the scan count register 22. next,
Scanning is started by setting the SCANM pinpoint to 1 and setting the scan mode to SSCSC 8 bits. In this way, the value of the target register is brought to the scan register 21. Next, data to be rewritten is set from the CPU t into the scan register 21. Thereafter, a scan operation is performed and the rewritten data is returned to the original register.

Next, a procedure for reading data from the RAM and replacing W will be explained. In the case of reading, the address is rewritten using a scan operation in order to set the value of the address register of the target RAM to the rh-fixed address.

Next, ALTM of the scan mode register 24 is set to 0 to set the RAM read mode. RA targeted at the same time
Select one piece of M to R, Ml, RAM2. Specify using each bit of RAM3. After that, scan mode register 2
STΔT of 4? Set the T bit to 1. As a result, the data to be referenced is read and sent to the output register of the RAM. Perform a scan operation on the data in this register; (scan up to scan register 21゛,
If you read this information via FMD5, the CPU
Know the contents.

Next, the case of rewriting data in the RAM will be described below.

First, an address to be referenced is set in the address register of the target RAM using a scan operation. Next, write data is sent to the input register of the target RAM by a scan operation. Then, the LTM bit of the scan mode register 24 is set to 1, and the RAM is set to rewrite mode. At the same time, RAM1. RAM2. RAM selection is performed using 3 bits of RAM3. Finally, by setting the 5TART bit of the scan mode register 24 to 1, the data in the RAM is erased, and the data specified by the CPU 1 is written into the RAM.

As described above, the present invention is a method for maintaining the adapter by accessing the adapter control register group in the adapter 2 from the CPUI side using only the data transfer bus connecting the adapter 2 and the CPUI.

〔Effect of the invention〕

According to the present invention, maintenance of the adapter can be performed without providing a dedicated interface for maintenance, which has the effect of reducing the cost of the computer system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a computer system J according to the adapter maintenance method of the present invention. FIG. 2 is a configuration diagram showing the relationship between the adapter control register group and the adapter and the system according to the adapter maintenance method of the present invention. Figure 3 is a configuration diagram of the scan mode register of the present invention, and Figure 4 is a configuration diagram of a computer system J~ according to the conventional adapter maintenance method in which a maintenance-only interface is installed. C
PU), 2...Adapter, 3...Data transfer bus, 4...Main storage device, 5...Field maintenance device, 6...Interface for maintenance only, 21...Scan register, 22...Scan count register, 23...Scan control register, 24...Scan mode register, 25-30...Flip-flop.

Claims (1)

[Scope of Claims] An adapter (2) that exclusively executes control related to input/output transfer according to a startup command from a central processing unit (CPU) (1), and notifies at least the CPU (1) of the end of the transfer; Storage means (25 to 3) provided inside the adapter (2)
0) and an adapter control register group (2
1, 22, 23, 24), and the adapter control register group (21, 22, 2
3 and 24) by accessing each register from the CPU (1), setting the storage means (25 to 30) inside the adapter (2) connected to the scan loop (31) to a request state; After operation, the internal state of the adapter (2) is transmitted to the C through the scan register (21).
A maintenance method for an adapter, comprising: a control means executed using a data transfer bus (3) connected between a PU (1) and the adapter (2).