JPH02267624A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPH02267624A
JPH02267624A JP1088296A JP8829689A JPH02267624A JP H02267624 A JPH02267624 A JP H02267624A JP 1088296 A JP1088296 A JP 1088296A JP 8829689 A JP8829689 A JP 8829689A JP H02267624 A JPH02267624 A JP H02267624A
Authority
JP
Japan
Prior art keywords
register
bit
registers
write
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1088296A
Other languages
Japanese (ja)
Other versions
JP2695463B2 (en
Inventor
Shinsuke Abe
阿部 信介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1088296A priority Critical patent/JP2695463B2/en
Publication of JPH02267624A publication Critical patent/JPH02267624A/en
Application granted granted Critical
Publication of JP2695463B2 publication Critical patent/JP2695463B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To attain the operation of bits just by writing the necessary data into a pair of registers by giving a write inhibiting or granting function to one of both registers capable of the simultaneous accesses for the bit corresponding to the other register. CONSTITUTION:When a certain bit of an A register 1 is 1, for example, the write is inhibited to the corresponding bit of a B register 2. Then this write is granted when the bit of the register 1 is 0. Here it is supposed that both registers 1 and 2 have the initial value 0H. Under such conditions, 5FH is written at one time to both registers 1 and 2. Thus the register 2 is inhibited to perform the write to the bit whose corresponding bit of register 1 is 1 owing to 5H of register 1; the bit is kept at initial value 0. While the register 2 is granted to perform the write to the bit whose corresponding bit is 0. Therefore the initial value is rewritten to 1 from 0 and the value of the register 2 is finally set at AH. As a result, the operation of bits is attained just with the write of a single time to both registers 1 and 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マイクロコンピュータ(以下、マイコンと
称す)に関し、特にそのレジスタのビット操作の改良に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microcomputers (hereinafter referred to as microcomputers), and particularly relates to improvements in bit operations of registers thereof.

〔従来の技術〕[Conventional technology]

従来のマイコンのビット操作の例として、第2図のフロ
ーチャートを用いて説明する。あるレジスタの特定ビッ
トをセット、クリアするなどのビット操作は、まずレジ
スタの値を読出しくステップS1)、その値に対し何ら
かの処理を行い(ステップS2)、再度読み出したレジ
スタに処理を施した値を書き込む(ステップ33)こと
によって行われる。
An example of bit manipulation in a conventional microcomputer will be explained using the flowchart shown in FIG. To perform bit operations such as setting or clearing a specific bit in a register, first read the value of the register (step S1), perform some processing on that value (step S2), and read out the processed value again in the register. (step 33).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマイコンのビット操作は以上のように行なわれて
いるので、ビット操作のためのオーバーヘッドが無視で
きず、リアルタイム性の高い用途には追随できないなど
の問題点があった。
Since bit operations in conventional microcomputers are performed as described above, the overhead for bit operations cannot be ignored, and there have been problems such as the inability to keep up with high real-time applications.

この発明は、上記のような従来のものの問題点を解消す
るためになされたもので、レジスタのビット操作に関す
るオーバーヘッドをなくすことができるマイクロコンピ
ュータを得ることを目的とする。
The present invention has been made to solve the problems of the conventional devices as described above, and an object of the present invention is to provide a microcomputer that can eliminate the overhead associated with register bit operations.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に関わるマイクロコンピュータは、同時にアク
セス可能な一対のレジスタの一方に、これに対応した他
方のレジスタの各ビットへの書き込み禁止あるいは許可
を制御する機能を持たせるようにしたものである。
In the microcomputer according to the present invention, one of a pair of registers that can be accessed at the same time has a function of controlling whether or not to write to each bit of the corresponding register.

〔作用〕[Effect]

この発明におけるマイクロコンピュータは、同時にアク
セス可能なレジスタをもち、一方のレジスタが他方のレ
ジスタの書き込み許可あるいは禁止をビット対応で指定
できるため、2つのレジスタへの1度の書き込みだけで
ビット操作が可能となる。
The microcomputer in this invention has registers that can be accessed simultaneously, and one register can specify whether or not to enable or disable writing to the other register in a bit-based manner, so bit operations can be performed by just writing to two registers once. becomes.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例によるマイクロコンピュータ
を示し、本実施例ではマイコンは4ビツトをデータの最
小単位とし、8ビット同時にアクセス可能であるものと
している0図において、1゜2は同時にアクセス可能な
1対のレジスタであり、1はレジスタ2の書き込みの禁
止あるいは許可を制御するAレジスタであり、図示しな
いデコータおよびマスク回路によりこの機能を実現して
いる。
FIG. 1 shows a microcomputer according to an embodiment of the present invention. In this embodiment, the microcomputer uses 4 bits as the minimum unit of data and can access 8 bits simultaneously. They are a pair of accessible registers, and 1 is an A register that controls write inhibition or permission of register 2, and this function is realized by a decoder and a mask circuit (not shown).

また、2はAレジスタlの内容によってその書き込みが
制御されるBレジスタである。なお、図中の3はレジス
タ1,2のビットがそれぞれ対応していることを示して
いる。
Further, 2 is a B register whose writing is controlled by the contents of A register l. Note that 3 in the figure indicates that the bits of registers 1 and 2 correspond to each other.

次に上記実施例の動作について説明する。Next, the operation of the above embodiment will be explained.

例えばAレジスタ1のあるビットが“1”であれば、そ
のビットに対応するBレジスタ2のビットへの書き込み
が許可され、逆にO”であれば書き込みが許可されると
する。ここで、Aレジスタ1. Bレジスタ2共に初期
値が’OHJであったとする。この両レジスタに同時に
「5FH」を書き込むと、Bレジスタ2はAレジスタ1
に設定された「5M」によって「1」と設定されたビッ
トへの書き込みは禁止されて初期値の「0」のままであ
り、r□、と設定されたビットへの書き込みは許可され
るので、初期値の「0」から「1」へ書き換えられる。
For example, if a certain bit in A register 1 is "1", writing to the bit in B register 2 corresponding to that bit is permitted, and conversely, if it is "O", writing is permitted.Here, Assume that the initial values of both A register 1 and B register 2 are 'OHJ.If you write "5FH" to both registers at the same time, B register 2 becomes A register 1.
Writing to the bit set to "1" is prohibited by "5M" set to , and the initial value remains "0", and writing to the bit set to r□ is permitted. , the initial value "0" is rewritten to "1".

よって最終的にBレジスタ2の値は「AM」となる。Therefore, the value of B register 2 finally becomes "AM".

このように、本実施例によれば、同時にアクセス可能な
1対のレジスタの一方に他方のレジスタの対応するビッ
トの書き込みを禁止あるいは許可する機能を持たせるよ
うにしたので、該1対のレジスタに所要のデータを書き
込むだけで、ビット操作を実現でき、従来のリード・モ
ディファイ・ライト動作による操作で問題となっていた
、オーバーヘッドを解消できる。
In this way, according to this embodiment, one of a pair of registers that can be accessed simultaneously has the function of inhibiting or permitting writing to the corresponding bit of the other register. Bit operations can be performed simply by writing the required data into the memory, eliminating the overhead that was a problem with conventional read-modify-write operations.

なお、上記実施例では8ビツトマイコンを例にとって説
明したが、他のビット長であってもよく、上記実施例と
同様の効果を奏する。
Although the above embodiment has been explained using an 8-bit microcomputer as an example, other bit lengths may be used and the same effects as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係るマイクロコンピュータに
よれば、同時にアクセス可能なレジスタノ一方に、ビッ
ト対応で他方のレジスタの書き込みを制御させる機能を
もたせたので、ビット操作をオーバーヘッドなしに処理
することができ、2つのレジスタへの一度の書き込みだ
けでビット操作が可能となる効果がある。
As described above, according to the microcomputer of the present invention, one of the registers that can be accessed at the same time has the function of controlling the writing of the other register in a bit-based manner, so that bit operations can be processed without overhead. This has the effect of making it possible to manipulate bits by just writing to two registers once.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるマイクロコンピュー
タのレジスタ構成を示す図、第2図は従来のマイクロコ
ンピュータにおけるビット操作のフローチャートを示す
図である。 図において、1はAレジスタ、2はBレジスタ、3はA
レジスタ1とBレジスタ2とのビット対応関係を示す。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a diagram showing a register configuration of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a diagram showing a flowchart of bit operations in a conventional microcomputer. In the figure, 1 is the A register, 2 is the B register, and 3 is the A register.
The bit correspondence between register 1 and B register 2 is shown. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)同時にアクセス可能な一対のレジスタを有するマ
イクロコンピュータにおいて、 上記一対のレジスタの一方に、これに対応する他方のレ
ジスタの各ビットへの書き込み禁止あるいは許可を制御
する手段を設けたことを特徴とするマイクロコンピュー
タ。
(1) A microcomputer having a pair of registers that can be accessed simultaneously, characterized in that one of the pair of registers is provided with means for controlling write inhibition or permission for each bit of the corresponding other register. microcomputer.
JP1088296A 1989-04-07 1989-04-07 Microcomputer Expired - Fee Related JP2695463B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1088296A JP2695463B2 (en) 1989-04-07 1989-04-07 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1088296A JP2695463B2 (en) 1989-04-07 1989-04-07 Microcomputer

Publications (2)

Publication Number Publication Date
JPH02267624A true JPH02267624A (en) 1990-11-01
JP2695463B2 JP2695463B2 (en) 1997-12-24

Family

ID=13938961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1088296A Expired - Fee Related JP2695463B2 (en) 1989-04-07 1989-04-07 Microcomputer

Country Status (1)

Country Link
JP (1) JP2695463B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203156A (en) * 1981-06-09 1982-12-13 Mitsubishi Electric Corp Computer for control
JPS63263527A (en) * 1987-04-22 1988-10-31 Hitachi Ltd Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203156A (en) * 1981-06-09 1982-12-13 Mitsubishi Electric Corp Computer for control
JPS63263527A (en) * 1987-04-22 1988-10-31 Hitachi Ltd Information processor

Also Published As

Publication number Publication date
JP2695463B2 (en) 1997-12-24

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