JPH02101552A - Address conversion buffer processing system - Google Patents

Abstract

PURPOSE:To improve a system processing speed by providing a shared area bit showing that they are shared by plural processors in respective entries of an address conversion table and reducing a redundant processing in an invalid processing. CONSTITUTION:The address conversion table 15 consists of a logical address, a physical address, access information and the shared area bits. For the shared area bits, '1' is set to areas which are shared and accessed by plural processors. When one of the processors 111-11N is started and the address conversion table 15 is altered, the shared bits are decided. Since they are not the shared areas if the bits are not '1', the invalid processing of an address conversion buffer TLB is not required, and a system immediately comes to a terminating processing. Consequently, the redundant processing in the invalid processing is eliminated and the system processing speed is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a processing method of an address translation buffer for a storage area shared by a plurality of processors in a multiprocessor computer system that shares main memory, redundancy in invalidation processing of the address translation buffer is disclosed. address translation in a multiprocessor computer system that supports a virtual address space that shares main memory and has an address translation buffer device for each processor. A buffer processing method in which a shared area bit is provided in each entry of the address translation table on the main memory to indicate that it may be shared by multiple processors, and the address translation table is invalidated for address translation buffers of other systems. In the invalidation process, the shared area bit is referred to and the invalidation process is selectively omitted.

[Industrial application field]

The present invention provides an address translation buffer (hereinafter referred to as TLB) for a storage area shared by multiple processors in a multiprocessor computer system that shares main memory.
(abbreviated as)).

As microprocessors have become cheaper and more sophisticated in recent years, such systems have been commercialized as systems using anywhere from a few to 20 microprocessors, and are widely used due to their high cost performance. It is expected that this will become possible.

However, processing for a buffer device, which is a cache for address translation that is normally provided in each processor, has redundant parts and degrades system performance. It was made by

[Prior Art] As an example, a memory sharing type multi-7'o setter system will be described. Generally, the configurations of these systems are almost the same as that shown in FIG. 2, and will be explained with reference to this.

In the figure, T LB (Translation
Look-asideBuffer) is a copy of a portion of the address translation table on main memory. The TLB and address translation table both contain a logical page address, its corresponding physical page address, and access information for that page (information such as whether it can be written or executed) for each address area of about several kilobytes called a page. ) is held as one entry, and is referenced to obtain the physical page address from the logical page address (see Figure 4).
.

In such systems, processes operate in logical space and make main memory references using logical addresses. Therefore, when the processor accesses the main memory, it is necessary to convert a logical address to a physical address, but searching the conversion table in the main memory each time requires a lot of processing time.

The TLB is a cache for speeding up this translation, and holds physical addresses corresponding to logical addresses recently referenced by the processor in the translation table. When an address is translated, first the TL
If B is searched and the logical address to be converted is found there, the physical address can be obtained without addressing the main memory. This significantly reduces main memory access time. For these reasons, TLBs are widely used in practical systems that perform address translation, regardless of whether they are multiprocessor or single processor.

In a multiprocessor system, if a certain area is shared by multiple processors, entries for the same logical address will be held in multiple TLBs. T.L.B.
is a copy of the address translation table in main memory, and specifies the mapping of physical addresses to logical addresses, access information, etc. Therefore, entries for the same logical address in each TLB are mapped to the same physical address and are accessed in the same way. If you don't keep the information,
Inconsistency occurs in processing.

However, there is a possibility that one of the processors having the same entry in the TLB may change the information of the entry in the address translation table on the main memory by page-out to the disk device or the like. In this case, contents other than the TLB of that processor will be inconsistent with the corresponding entry on the main memory. Therefore, in order to reflect this change to all processors, normally when a processor rewrites the address translation table in main memory, it always interrupts other processors and
The LB searches for and invalidates the entry for the corresponding logical address.

The invalidation process according to the conventional method is shown in FIG. Through this processing, when the same area is accessed again, an entry is newly read from the address translation table in the main memory, so it is possible to prevent inconsistencies in the contents of the TLB between processors.

[Problem to be solved by the invention]

However, in reality, areas that are shared and accessed by multiple processors are limited and can be specified before program execution. Conventionally, in such cases, there was no means for specifying and identifying a storage area shared by multiple processors, so when each processor changed its address translation table, it had to update the TLB to other processors. Even if there is no possibility that the entry is shared, as described above, the TLB of other processors is invalidated, resulting in wasted time.

The purpose of the present invention is based on the idea of providing a means for specifying an area that may be shared by multiple processors.
The object of the present invention is to reduce redundant processing in TLB invalidation processing and improve the processing speed of the system.

[Means for Solving the Problems] In the present invention, as illustrated in FIGS. 1 and 2, the main memory 14 is shared and each processor ((1)
~(N) A processing method for an address translation buffer in a multiprocessor computer system supporting a virtual address space having address translation buffer devices 121 to 12N in H1l to H11N, respectively, the main memory 14
A shared area bit is provided in each entry of the above address translation table 15 (S5), so that it can be determined from the value of the shared area bit whether or not there is a possibility that the entry may be shared by a plurality of processors. Then, when invalidating the address translation buffer of another system (S3), the shared area bit is referred to (S2), and if there is no possibility of the shared area, the invalidating process is omitted (S4). A translation buffer processing scheme is provided.

[For production]

The shared area bits provided on the conversion table described above are set or reset by the operating system dynamically in response to instructions from a user program when setting the logical space for the process or when executing the process. If it becomes necessary to change the address translation table in main memory as described above, the operating system refers to the shared area bit and disables other processors only if that bit is set. conduct.

〔Example〕

FIG. 1 is a flowchart of the processing process of the address translation buffer processing method as an embodiment of the present invention, FIG. 2 is a block diagram of the system to which the present invention is applied, and the address translation table of the embodiment is shown in FIG. - and a diagram illustrating the contents of the TLB is shown in FIG.

The system shown in FIG. 2 constitutes a multiprocessor system by a plurality of processors 111 to 11N, and the Kahai processors 111 to 11N each have TLBs 121 to 12.
N, these are connected by a shared bus 13, and a main memory 14 is connected to the shared bus 13. The main memory 14 is provided with an address conversion table for converting logical addresses into physical addresses. TLB is a cache that stores part of the address translation table. Address conversion table 1
As shown in Figure 3, field 5 consists of a logical address, a corresponding physical address, access information, and a 1-bit shared area bit (see the right end of Figure 3). be done. These are TLB as is.
However, storing the shared area bit in the TLB can be omitted.

The shared area bit is set to "lJ" for an area that is shared and accessed by multiple processors.

The process of the embodiment will be explained with reference to FIG. Assume that processing is started for one processor m, and the address translation table 15 is changed (processing step S1
), it is determined whether the shared area bit mentioned above is "1" (step S2). If it is not "1", it is not an area that is shared by multiple processors, and is therefore not an area that is used by other processors 111 to 11N other than processor m. ), and the process ends immediately (step S4). If the shared area bit is “1”, the TLB of other processors
In order to invalidate the entry, an interrupt is generated to other processors (processors 111 to 11N other than processor m) (step S3), and the interrupt processing routine is started to complete the invalidation process of the TLB entries of other processors. After that, the processing of processor m ends.

〔Effect of the invention〕

According to the present invention, redundant invalidation processing of address translation buffers of other processors can be omitted, and the processing speed of the system can be improved.

[Brief explanation of drawings]

FIG. 1 is a flowchart of a processing process for implementing an address translation buffer processing method as an embodiment of the present invention, FIG. 2 is a block diagram of a system to which the present invention is applied, and FIG. 3 is an embodiment of the method shown in FIG. Figure 4 is a diagram similar to Figure 3 explaining the conventional example, and Figure 5 is a diagram similar to Figure 1 showing the processing process of the conventional example. be. In the figure, 111 to 11N...processor, 121 to 12N...TLB. 13...Shared bus, 14...Main memory, 15...Address conversion table. Block diagram of the system to which the present invention is applied Processing process of the embodiment Fig. 1 Fig. 3 Processing process of the conventional example

Claims (1)

[Claims] The main memory (14) is shared, and the individual processors (111 to 111)
11N) to the address translation buffer device (121 to 12N)
) is a processing method for an address translation buffer in a multiprocessor computer system supporting a virtual address space having A shared area bit is set to indicate that there is a possibility that the
3), refer to the shared area bit (S2)
An address translation buffer processing method that selectively omits invalidation processing (S4).