JPH0883215A - Memory controller - Google Patents

Abstract

PURPOSE: To improve the performance and reliability of a system which has hierarchical memory structure. CONSTITUTION: This controller is equipped with a comparator 6 which decides a write-back or write-through process according to an access address, a register 5 which holds a comparison address, a non-caching mode flag, etc., a write-back/ write-through control circuit 4, and a forcible mode control circuit 7 which controls a non-caching process, etc. When the write-through process is decided because of write access and the non-caching mode is set, data in an object area of the write-through process are not cached in a high-order memory 2 and the write-access process is performed by using only a low-order memory 3. The write-back process can be performed for an area wherein high-speed memory access is required and the write-through process can be done for an area wherein the memory contents of a high and a low layer need to match each other; and the non-caching process where the data in the area of the write- through process are not stored in the high-order memory is actualized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system having a hierarchical memory structure, and more particularly to a memory controller suitable for improving system performance and reliability.

[0002]

2. Description of the Related Art In recent years, systems having a hierarchical memory structure have become mainstream in order to realize high-speed memory access. Usually, a part of the memory content of the lower layer is copied to the memory of the upper layer, and when the content of the upper memory is updated, the content of the lower memory is also updated by the write back process or the write through process. The write-back process only updates the upper memory contents, when the contents of the lower memory are newly copied to the upper memory, the updated memory contents are reflected in the lower memory, and the access destination contents existing in the lower memory Is a process of copying to the upper memory and performing write or read access, and although the memory contents do not match temporarily between the upper and lower layers, the memory access can be processed at high speed. On the other hand, in the write-through process, since the lower memory contents are updated at the same time as the upper memory contents are updated, the memory contents always match between the upper and lower layers, but it is difficult to process the memory access at high speed. For example, the "cache device" described in Japanese Patent Laid-Open No. 5-204754 is a write-through type cache device, which reduces the frequency of partial write access to the main storage device, which is a cause of performance degradation, and therefore a write block. In this case, the write data is combined with the signal indicating the rewriting of all bytes in the memory and the signal indicating the cache hit state at the time of write access, and the entire writing is performed in the main memory.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the technique described in Japanese Patent No. 754, although the cache system of the write-through system is used, the data consistency between the cache and the main memory is temporarily destroyed, and all the bytes in the write block are written. It is provided with a signal generation circuit for indicating rewriting and a write data synthesis circuit,
It must be controlled as part of the write-through operation. Therefore, it is difficult to improve the data consistency and the write-through processing performance. Furthermore, with this device,
In a system having a hierarchical memory structure, no consideration has been given to the processing when the upper memory becomes unusable due to some kind of failure, or the data write regulation of the write protected area. An object of the present invention is to improve such a problem, improve the performance and reliability of a system having a hierarchical memory structure, and flexibly control data writing in a write protected area when the upper memory becomes unavailable. It is to provide a memory control device that can handle the above. That is, write-back processing is executed for areas requiring high-speed access, write-through processing is executed for areas requiring data consistency, and data in the write-through processing target area is executed. Not stored in upper memory, non-
The purpose is to realize the caching process.

[0004]

In order to achieve the above object, the memory control device of the present invention, in a system having a hierarchical memory structure, when a memory write access occurs, write back processing and write are performed according to the value of the access address. A means for determining which of the through processing is to be performed (see FIG.
5) and 6), a means for controlling the write-back process and the write-through process (4 in FIG. 1), and a memory area to be the target of the write-through process are not taken into the upper memory (2 in FIG. 1) Means (5 in FIG. 1) for setting the non-caching mode in which processing is performed only in the memory (3 in FIG. 1)
And a means for instructing the control means to perform non-caching processing when the non-caching mode is set by the setting means (7 in FIG. 1). And a memory write access to the write-through processing area occurs,
If the caching mode is set, it is characterized in that access to the upper memory is suppressed and write access is performed only to the lower memory.

[0005]

According to the present invention, the write-back / write-through process is executed by judging the write-back / write-through process from each access address by the above-mentioned discrimination / control means. It is possible to perform the write-through processing for the areas where the matching of the memory contents between the areas is required. In addition, by setting the non-caching mode, for example, when the upper memory becomes unusable, the write-through processing area does not copy the contents of the lower memory to the upper memory, and always accesses only the lower memory. It is possible to realize non-caching processing. In addition to the write-back / write-through mode for the target memory area and the non-caching mode, a mode for forcibly performing write-back processing or write-through processing for all areas (for example, compulsory mode flag and compulsory mode control) Realized with a circuit)
In the case of providing, the write-back / write-through processing can be more efficiently mixedly controlled.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 is a request source for requesting access to a memory such as MPU, 2 is an upper memory, 3 is a lower memory, and memories (storage devices) 2 and 3 have a hierarchical structure. Further, 4 is a write back / write through control circuit for controlling the write back process and the write through process,
Reference numeral 5 denotes a comparison address that holds a division address for write-back / write-through processing, a compulsory mode flag indicating that the write-back / write-through processing is forcibly executed in all areas, and a non-caching mode flag.
Mode flag register, 6 is a comparator for comparing the access address and the cut-off address, 7 is a forced mode control circuit, 8 and 9 are access address selectors, 24
Is a lower memory write data selector. In the present embodiment, among the above devices, access address 10, write data 11, division address 13, upper memory read data 18, lower layer write data 20, 22, upper memory access address 21, lower memory access address 23, write The back access address 19 is used for connection, and the control signal 12 is used for the division address and mode flag of the register 5, the comparison result 14 and the mode flag 15 are used for the compulsory mode control circuit 7, and the processing mode control signal 16 is used for write back / write through control. The circuit 4 operates by controlling the access address selectors 8 and 9 and the lower memory write data selector 24 by the selector control signal 17, respectively.

Next, the processing operation of this embodiment will be described.
The request source 1 outputs a write access address 10 and write data 11 to the upper memory 2 to request a write access. If data corresponding to the write access address 10 exists in the upper memory 2, the write data 11 is updated. At the same time, the access address 10 is also input to the comparator 6, and it is determined which of the write-back / write-through processing is to be performed on the lower memory 3. This comparison / determination operation compares the preset division address of the comparison address / mode flag register 5 with the access address 10 and outputs a comparison result 14, and if the access address is less than or equal to the division address, the lower order A control signal 16 for causing the memory 3 to execute the write-back process and executing the write-through process for the lower memory 3 when the access address is larger than the division address.
Is output from the forced mode control circuit 7. The above operation is performed when the forced non-caching process or forced write back process / forced write through process is not set by the mode flag in the register 5.

For example, when write-through processing is specified for the lower memory 3, the access address selectors 8 and 9 are selected by the selector control signal 17 output from the control circuit 4.
To connect the access address 10 to the upper memory 2 and to control the lower memory write data selector 24 to connect the write data 11 to the lower memory 3 to perform a write operation to the lower memory 3 as well, and perform a write through process. To execute. When write back processing is specified for the lower memory 3, the write operation is performed only for the upper memory 2, and then the upper memory 2 is accessed by another access.
When the memory contents of are replaced, the following operations are executed. The control circuit 4 outputs the selector control signal 17 and the write back access address 19. The selector control signal 17 controls the access address selector 8 to connect the write back address 19 to the upper memory 2. The upper memory 2 outputs upper memory read data 18 corresponding to the write back address 19. Next, data 18
To the lower memory 3, the selector control signal 17
Then, the access address selector 9 is controlled to connect the write-back address 19 to the lower memory 3, and the lower memory write data selector 24 is controlled to connect the lower layer write data 20 to the lower memory 3 so that the lower memory 3
A write back process is executed for. Then, the contents of the access destination existing in the lower memory 3 are copied to the upper memory 2 and accessed. By the above operation, write back processing or write through processing is divided according to the access address.

Next, a non-caching process will be described in which the memory area which is the target of the write-through process is not taken into the upper memory 2 but is processed only in the lower memory 3. The mode flag of the register 5 is preset to the non-caching mode by the control signal 12.
When a write access occurs in this state, the comparator 6 operates and the comparison result 14 is output.
If 4 indicates access to the memory area that is the target of the write-through processing, the compulsory mode control circuit 7 outputs the processing mode control signal 16 indicating the non-caching mode. As a result, the write access to the upper memory 2 is suppressed and the write access to only the lower memory 3 is executed.

Further, the operation of always executing the write-back process or the write-through process for all the areas will be described. The mode flag of the register 5 is set in advance to either the forced write-back mode or the forced write-through mode by the control signal 12.
When a write access occurs in this state, the comparator 6 operates and the comparison result 14 is output.
Regardless of 4, the processing mode control signal 16 according to the state of the mode flag of the register 5 is output, and the write-through / write-back processing for all the above areas is executed. With the above operation, the write back process or the write through process is always executed regardless of the access address.

In the system shown in this embodiment, a one-chip MPU system in which a part of the arithmetic unit and the hierarchical memory structure are housed in one chip, and the arithmetic unit and the hierarchical memory structure are composed of separate chips. System, and a system in which a part of the hierarchical memory structure is an external storage device. Further, in the case of realizing the non-caching mode, it may be configured such that whether the normal write-through process or the non-caching process is performed is determined by the access address. Further, although the method of setting the mode flag in the register 5 is used in the present embodiment, for example, a method of setting the mode by an external pin may be used.

[0012]

According to the present invention, in a system having a hierarchical memory structure, write-back processing is performed for areas requiring high-speed memory access, and for areas requiring memory content consistency between upper and lower layers. By performing each write through process, it is possible to improve the system performance and reliability. In addition, since the contents of the lower memory are not copied to the upper memory during write-through processing, non-caching processing that always accesses only the lower memory can be realized, so if the upper memory becomes unavailable or write protection is performed. It is possible to flexibly comply with area data writing restrictions. When a mode for forcibly implementing the write back / write through processing in all areas is provided, the write back / write through processing can be mixed and controlled more efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control system according to an embodiment of the present invention.

[Explanation of symbols]

1: a request source requesting access to a memory such as MPU,
2: Upper memory, 3: Lower memory, 4: Control device, 5:
Separate address for write back / write through processing,
Comparison address / mode flag register holding forced write-back / write-through mode flag and non-caching mode flag, 6: comparator, 7: forced mode control circuit, 8, 9: access address selector, 1
0: access address, 11: write data, 12: control signal, 13: division address, 14: comparison result, 1
5: Mode flag, 16: Processing mode control signal, 17:
Selector control signal, 18: upper memory read data,
19: write back access address, 20, 22: lower hierarchy write data, 21: upper memory access address, 23: lower memory access address, 24: lower memory write data selector.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Murashima 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Hitachi Ltd. Office Systems Division (72) Inventor Toshiro Akiyama 10-22 Sakae, Naka-ku, Nagoya-shi, Aichi No. in Nihon Chubu Software Co. Ltd.

Claims (1)

[Claims] 1. In a system having a hierarchical memory structure, when a memory write access occurs, a means for discriminating between write back processing and write through processing depending on a value of an access address, and write back processing and write through. Non-processing means that controls the process and the memory area that is the target of the write-through process is not taken into the upper memory, but is processed only in the lower memory.
A means for setting a caching mode and a means for instructing the control means to perform non-caching processing depending on the result of the discrimination and the presence / absence of the setting are set. If the non-caching mode is set in, the instruction means instructs the control means to perform the non-caching process, and the access to the upper memory is suppressed and only the lower memory is write-accessed. A memory control device characterized by being configured.