JPH10133948A - Cache memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput by reducing access time to a main storage device. SOLUTION: A processor 10 is provided with a locking instruction control part 12 instructing a locked state prohibiting the rewriting of a cache link of a cache memory 30 and a free instruction control part 13 for releasing the locked state. A locked bit area 40 for setting the locked or free state of the cache line is provided in the cache directory 37 of the cache memory 30. At the time of cache hit, access to the cache line of the cache memory 30 is executed. At the time of cache mis-hit, the cache memory 30 is bypassed to access the main storage device when the cache line is in the locked state, but read replacing or write allocate is executed when the cache line is in the free state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory device located between a processor and a main storage device in a data processing system or the like.

[0002]

2. Description of the Related Art For example, in a data processing system such as a computer system, a cache memory capable of operating at a higher speed than a main storage device is provided between a main storage device and a processor. In order to improve the processing speed of a processor by temporarily storing data to be accessed, a configuration is widely adopted.

As a device (cache memory device) using this cache memory, a device called a write-back method (write-back cache) has been used. In the write-back method, when data is written by the processor, only the data in the cache memory is updated, and the main storage device is not updated. Then, the data updated in the cache memory is written back (written back) from the cache memory to the main storage device, for example, when the directory of the cache memory is updated.

An example of a cache memory device using the above-described write-back method will be described below. 10, the processor 60 includes an address control unit 11, an interrupt control unit 15, an instruction decoder 61, a read / write control unit 16, and the like. The cache memory 70
It comprises a read / write instruction unit 36, a cache directory 71, a comparator 42, a data cache 46 and the like. Further, the processor 60 and the cache memory 70 are connected by an address line 21, a data line 24, a read / write line 26, and the like.

[0005] The address control unit 11 constituting the processor 60 has an address 2 for executing processing in accordance with an instruction.
Outputs 1. The read / write control unit 16 determines whether the operation for executing the process is a read or write operation by the read / write line 26.
Output through The instruction decoder 61 analyzes an instruction based on the data 24 and controls the operations of the address control unit 11 and the read / write control unit 16 based on the result.
As a special operation, when the interrupt 25 is requested, the interrupt control unit 15 controls the interrupt of the address control unit 11 and the read / write control unit 16. Also,
In the cache memory 70, the address 21 from the address control unit 11 of the processor 60 is the address 31
, The tag address 32 and the set address 33
And the cache directory 71
Alternatively, it is sent to the comparator 42.

Here, the tag address 32 is used for comparison with tag data 72 registered in the cache directory 71. Also, set address 3
Reference numeral 3 is used to specify a line address (line number) of the cache directory 71.

The cache directory 71 is
It has a depth corresponding to the set address 33, and has tag data 72, a valid bit 73 and a dirty bit 74. The tag data 72 is the value of the tag address 32 registered in the cache directory 71 by cache read replace or cache write allocate. The valid bit 73 indicates whether the cache line indicated by the set address 33 is valid / invalid.
d) is shown. Further, the dirty bit 74 is a bit unique to the write-back method, and
If the data of 0 and the main storage device 50 match, this indicates clean, and if they do not match, it indicates dirty.

[0008] The comparator 42 compares the tag data 72 of the cache directory 71 with the tag address 32 requested by the processor 60. If they match, that is, if the requested block exists in the cache memory 70, the cache
Hit (logical value "1"), data cache 4
6 is accessed. The data cache 46 is a memory for holding data access information from the processor 60. Also, tag data 7
If 2 does not match the tag address 32, it is a cache miss hit (logical value "0"), and a read replace operation or a write allocate operation is performed. At this time, if the line of the cache directory 71 to be replaced is dirty, data is written back to the main storage device 50 in order to maintain consistency between the cache memory 70 and the main storage device 50.

Next, the operation of this conventional example will be described with reference to FIGS. In the following description, for convenience, the bus width and the size of the cache line are assumed to be equal. That is, for example, when the bus width is 8 bits, the size of the cache line is 1 byte, and when the bus width is 32 bits, the size of the cache line is also 4 bytes (1 WOW).
rd).

FIG. 11 shows what operation or processing is executed depending on the state of the cache memory 70 when a read or write request is issued from a processor 60 to a certain cache line. It is. Of the execution operations shown in FIG. 11, the operation at the time of a write request will be described with reference to FIG. 12, and the operation at the time of a read request will be described with reference to FIG.

First, referring to FIG. 12, a write operation is performed as in the following (1) to (3). (1) Cache hit In this case, since the address 21 requested by the processor 60 is registered in the cache memory 70, data is directly written to the cache memory 70 (cache data write operation). In this case, since a mismatch occurs between the cache memory 70 and the main storage device 50, the dirty bit 74 becomes dirty regardless of the state of the previous cache line (FIG. 1).
2 (a)).

(2) Cache miss hit (cache line is clean) In this case, since the address requested by the processor 60 is not registered in the cache memory 70, the currently registered cache directory 71 Need to be replaced. At this time, the operation differs depending on whether the state of the cache line in the currently registered cache directory 71 is clean or dirty. When the cache line is clean, since the data in the cache memory 70 and the data in the main storage device 50 match, the data is directly written into the cache memory 70 and the cache directory 71 is re-registered at the same time. (Cache write allocate operation). At this time, the written cache line becomes dirty (FIG. 12B). The operation when the cache line is dirty will be described in the following (3).

(3) Cache miss hit (cache line is dirty) In this case, since the data in the cache memory 70 and the data in the main storage device 50 do not match, before replacing the address of the cache directory 71, The data of the registered cache line is written back to the main storage device 50 (write-back operation; cycle 0 in FIG. 12C). Next, the data is directly written into the cache memory 70, and at the same time, the cache directory 71 is re-registered (cache write allocate operation). In this case, the cache line becomes dirty (FIG. 1).
2 (c) cycle 1).

Next, referring to FIG. 13, the read operation is performed as in the following (11) to (13). (11) Cache hit In this case, the requested address is stored in the cache memory 70
, The data is directly read from the cache memory 70 (cache data read operation). At this time, the state of the cache line retains the previous state of either clean or dirty (FIG. 13).
(A)).

(12) Cache miss hit (cache line state is clean) In this case, since the requested address is not registered in the cache memory 70, the cache directory 71 is replaced with the currently registered cache directory 71. Need to replace the address. At this time, the operation differs depending on whether the state of the cache line in the currently registered cache directory 71 is clean or dirty.
If the state of the cache line is clean, the data in the cache memory 70 and the data in the main storage device 50 match, so that the data at the requested address is read from the main storage device 50 and , And the cache directory 71
Is re-registered (cache read replace operation). In this case, the cache line state becomes clean (FIG. 13B).

(13) Cache miss hit (cache line state is dirty) In this case, since the data in the cache memory 70 and the data in the main storage device 50 do not match, the cache directory 7
Before the re-registration of 1, the data of the currently registered cache line is written back to the main storage device 50 (write-back operation; cycle 0 in FIG. 13C). Next, the data at the requested address is read from the main storage device 50, and at the same time, the cache memory 70 is written and the cache directory is re-registered (cache read / write).
Replace operation). At this time, the cache line state becomes clean (cycle 1 in FIG. 13C).

In the cache memory shown in FIG. 10, between the stack stacking operation and the pulling-out operation, a write / write operation to the same cache line by another address is performed.
The operation when the access is performed will be described. Referring to FIG. 14, the operation in this case is as follows (21) to (23). (21) Stacking on the stack (assuming a cache hit) Since this is a cache hit, stack data is directly stacked on the cache memory. At this time, the state of the cache line is dirty (FIG. 14).
(A)).

(22) Since a write access to the same cache line by another address results in a cache miss hit, the data of the currently registered cache line is first written back to the main storage device 50 (FIG. 14 (b) ) Cycle 0).
Next, a write access is performed, and the cache memory 70
And re-register it in the cache directory. At this time, the state of the cache line is dirty (cycle 1 in FIG. 14B).

(23) Extraction from the stack This access also results in a cache miss hit.
First, the data of the currently registered cache line is written back to the main storage device 50 (cycle 0 in FIG. 14C). Next, original read access is performed, and data is read from the main storage device 50. At the same time, data is written to the cache memory and the cache directory is re-registered. At this time, the state of the cache line is clean (cycle 1 in FIG. 14C).

Here, in the above cache memory, the ratio of the access time largely related to the processing capability of the processor is 1 to 5 or more in the ratio of cache hit to cache miss (access to the main storage device). Would. This ratio also increases as the size of the cache line increases. Then, as described above, by adopting the write-back method of writing only to the cache memory without writing to the main storage device, access to the main storage device can be reduced as much as possible to improve processing performance.

[0021]

However, the above-described write-back cache memory has the following problems. That is, in the write-back method, when the cache directory in the cache memory is replaced, it is necessary to write back the previously registered data to the main memory, and further, the written back data is accessed again. If so, the main storage must be accessed.

And stacking / drawing stacks,
For data that is frequently used and accessed like updating / referencing a table, for example, after stacking or updating the table, the cache line is updated and the cache directory is replaced by access in another process. If the above situation occurs,
Since the number of accesses to the main memory due to the replacement of the cache memory increases, the access time increases and the processing performance decreases. Also, in this case, the number of cache hits is reduced by updating the cache line. Furthermore, since the write-back method is used, an extra overhead of writing back to the main storage device occurs, and the access time is further increased. This is particularly significant in a direct mapping system in which the set address has only one way (one way set associative mapping system).
This is a factor that lowers the processing capacity. Further, in this case, the write allocate operation is performed by the cache memory from the main storage device.
Since data is written to the cache memory after loading in line units, the overhead is further increased.

For example, if the ratio of cache hit to access time to the main memory per line is 1 clock to 5 clocks, in the example described above, 17 (1+
(5 + 1) + (5 + 5)) clocks. The access to the main storage device takes 15 clocks. Also, of these, 10 clocks are required for access to write back to the main storage device in order to maintain consistency at the time of a miss hit.

In the cache memory exemplified above, the access time to the main storage device is relatively short because the bus width (the number of bits) and the cache line size are equal, but the cache line size is different from the bus width. 2n times, the access to the main memory, in particular, the operation of writing back to the main memory becomes high, and the access time increases. Furthermore, in this case, the write-allocate operation
After the data is loaded from the main storage device in units of cache lines, the data is written to the cache memory, so that the overhead is further increased.

The write-allocate operation at the time of a cache miss / hit is performed with respect to the bus width.
If the size of the line is large, it is necessary to load the cache memory from the main memory in units of cache lines before performing a cache write. This causes an increase in access to the main storage device and an increase in access time. Here, the above drawback is a problem that occurs when frequently used and accessed data is evicted from the cache memory and replaced with other data.

An object of the present invention is to provide a cache memory device capable of improving the cache hit rate, reducing the number of accesses to the main storage device, and improving the processing performance.

[0027]

According to the present invention, there is provided a cache memory device of a write-back system provided between a processor and a main storage device, wherein the processor reads / writes data from / to the main storage device. A memory unit having at least one address for temporarily holding data to be written, a memory management unit for controlling reading / writing of data at each address of the memory unit, and data replacement for each address of the memory unit. A lock control unit that sets either a lock state in which data cannot be replaced or a free state in which data can be replaced, and the memory management unit stores the processor address in a specific address of the memory unit when the memory unit is in a locked state. When a read / write access is made from the In the case of a cache miss hit that does not exist in the serial address, characterized in that to bypass the access to the main storage device.

In the present invention, the lock control section shifts each address of the memory section from the free state to the locked state or from the locked state to the free state in accordance with an instruction from the processor. Also, for example, the transition from the free state to the locked state of a specific memory in the memory unit is performed when the processor writes to that address. Further, the transition from the locked state to the free state of a specific address in the memory unit is performed when a cache hit where data corresponding to read / write access from the processor exists at this address, or when reading from the processor. Done in

Further, the lock instruction for shifting from the free state to the locked state or the free instruction for shifting from the locked state to the free state is frequently issued, for example, when stacking or pulling out a stack. This is performed for frequently accessed data used for

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a cache memory device according to the present invention will be described below. The cache memory device according to the embodiment shown in FIG. 1 includes a processor 10, a cache memory 30, and an address line 21 and a lock instruction line 2 between the processor 10 and the cache memory 30.
2. Free instruction line 23, data line 24, interrupt line 2
5, read / write lines 26, and the like.

The processor 10 includes an address control unit 11,
It comprises a lock instruction control unit 12, a free instruction control unit 13, an instruction decoder 14, an interrupt control unit 15, a read / write control unit 16, and the like. Cache memory 30
Are a lock instruction unit 34, a free instruction unit 35, a read / write instruction unit 36, a cache directory 37, a comparator 42, a bypass determination unit 43, a directory replacement determination unit 44, a lock bit control unit 45, a data cache 46, and the like. Consists of

Here, the processor 10 is connected to the data line 24
The instruction read through the instruction is analyzed by the instruction decoder 14. As a result of this analysis, if it is a normal access, it notifies the address control unit 11 and the read / write control unit 16 respectively. Further, as a result of the analysis, for example, if the operation is a write operation to the stack such as a store instruction to the stack and a store instruction with a lock instruction, the lock instruction control unit 12 is notified (write operation with a lock instruction). Further, as a result of the analysis, for example, in the case of a read operation such as a load instruction from the stack or a load instruction with a free instruction, the read instruction control unit 13 is notified (read operation with a free instruction).
The address control unit 11 outputs an address 21 to be executed next.

The read / write control unit 16 determines whether the process to be executed next is a read operation or a write operation by the read / write line 2.
Output through 6. The lock instruction control unit 12 outputs a status through the lock instruction line 22 during a write operation with a lock instruction. The free instruction control unit 13
The status is output through the free instruction line 23 at the time of the write operation with the free instruction. As a special operation, when an interrupt is requested through the interrupt line 25, the interrupt control unit 15 operates and the address control unit 11, the read /
It notifies the write control unit 16 and the lock instruction control unit 12 (write operation with lock instruction).

The cache memory 30 is
From the address line 21 via the address line 21
The address is divided into an address 32 and a set address 33, and these are sent to the cache directory 37 and the comparator 42, respectively. 10, the tag address 32 is compared with the tag data 38 registered in the cache directory 37, and the set address 33 is the line address (line number) of the cache directory 37. ) Is used to specify each.

The cache directory 37 has a depth equal to the set address 33 and has the tag data 3
8, valid bit 39, lock bit 40 and dirty bit 41. Tag data 38 is
Cache directory 37 by cache read replace or cache write allocate
Is the value of the tag address 32 registered in.

The valid bit 39 indicates whether the valid (va) of the cache line indicated by the set address 33 is valid.
lid) / invalid. Lock bit 40 indicates the locked / free state of the cache line. The dirty bit 41 indicates that data between the cache line and the main storage device 50 match (clean) / mismatch (dirty). The comparator 42 compares the tag data 38 in the cache directory 37 with the tag address 32 requested by the processor 10 to determine a cache hit / miss hit. Is output. In the case of a cache miss hit, the state of the lock bit 40 is confirmed as follows.

That is, if the lock bit 40 is in the locked state, the bypass determiner 43 determines that the cache is a bypass, and outputs a logical value “1” as a BYPASS signal. If it is in the free state, the cache directory is to be replaced. Therefore, the directory replacement determining unit 44 determines that the cache read / replace or cache write allocate is performed, and outputs a logical value “1” as a REPLACE signal. I do.

Further, the lock / bit control unit 45 sends the lock instruction unit 34 and the free instruction unit 3 from the processor 10.
5. The state of the lock bit of the cache line is controlled by the information output through the read / write instruction unit 36 and the comparator 42, the bypass determiner 43, and the directory replacement determiner 44. "1"
, And if free, outputs a logical value “0”. Note that, as described above, the data cache 46
This is a memory that holds data access information from the processor 10.

The control of the lock bit in the cache memory of this embodiment will be described with reference to FIGS.
First, referring to FIG. 2, stacking (store) of a stack
/ Lock bit control at the time of pull-out. (31) In the case of stacking, the processor 10 automatically requests a lock instruction during a write operation on the stack. At this time, if the state of the cache line indicated by the set address 33 is free, the lock bit 40 is changed to the locked state at the end of the write operation on the stack (FIG. 2A).

(32) In the case of pulling out a stack, the processor 10 automatically requests a free instruction during a read operation on the stack. At this time, the set address 33
If the cache line indicated by is a cache hit and is in the locked state, the lock bit 40 is changed to the free state at the end of the read operation on the stack (FIG. 2B).

The operation of the lock bit control at the time of executing the store with lock instruction (write instruction with lock instruction) / load with free instruction (read instruction with free instruction) is similar to the above-described lock bit control.
This is performed as shown in FIG. 2A or 2B. The store instruction with a lock instruction and the load instruction with a free instruction are instructions newly added to the processor 10 in the present invention, and are different from the lock bit control described above in that they can be performed programmably. .

FIG. 3 shows the state transition of the lock bit 40. That is, the lock bit 40 becomes the next (4)
The state transitions as shown in 1) to (44). (41) Transition from Free State to Locked State A write operation with a lock instruction is performed on the cache line in the free state S2, and the locked state S
1 (S3). Note that when the processor 10 executes a stack stack or a store instruction with a lock instruction, the cache memory 30 determines whether it is a hit or a miss hit. If a hit occurs, data is written to the cache memory 30 and the cache directory 37 is locked at the same time. In the case of a miss hit, it is confirmed that the cache directory 37 is in a free state, and a write allocate operation is performed, and at the same time, a lock state is set.

(42) Lock State In the case where a write operation with a lock instruction, a normal read / write operation, and a read operation with a free instruction in the case of a miss hit are performed on the cache line in the lock state S1, Then, the locked state S1 is held (S5). Note that, in response to an access request from the processor 10, the cache memory 30 determines whether it is a hit or a miss hit. If the hit is other than a read with a free instruction, the cache memory 30 is accessed. At this time, the cache directory 37 remains locked. In the case of a miss hit, it is confirmed that the cache directory 37 is locked, the cache is bypassed, and the main storage device 50 is accessed. At this time, the cache directory 37 remains locked.

(43) Transition from the Locked State to the Free State The cache line in the locked state S1 is shifted to the free state S2 by executing a read operation with a free instruction at the time of a cache hit (see FIG. 4). S4). When the processor 10 executes the stack instruction or the load instruction with the free instruction, the cache memory 3
0 determines a hit or a miss hit. And miss
If it is a hit, the locked state is not released (cache bypass operation is performed). In the case of a hit, data is read from the cache memory 30 and the cache directory 37 is set in the free state at the same time.

(44) Free State When a read with a free instruction and a normal read / write operation are performed on the cache line in the free state S2, the free state S2 is held (S
6). Note that, in response to an access request from the processor 10, the cache memory 30 determines whether it is a hit or a miss hit. If the hit is other than a write with a lock instruction, the cache memory 30 is accessed. At this time, the cache directory 37 remains free. In the case of a miss hit other than a write with a lock instruction, a read replace or write allocate operation is performed. At this time, the cache directory 37 remains free.

Next, the specific operation of the cache memory according to the embodiment will be described with reference to FIGS. In addition,
In the following description, for convenience, it is assumed that the bus width is equal to the size of the cache line.

FIG. 4 shows the cache memory of the cache memory 30 when each access such as a normal write, a normal read, a write with a lock instruction, and a read with a free instruction is executed from the processor 10 to a cache line. Indicates what kind of execution operation will be performed depending on the state. Further, each execution operation in FIG.
The details will be described below with reference to FIGS.

First, a normal write operation is performed as shown in the following (51) to (54) with reference to FIG. (51) Cache hit In this case, data is directly written to the cache memory 30 (cache data write operation). At this time, the lock bit 40 remains as it was before execution, and the dirty bit 41 enters a dirty state (FIG. 5).
(A)).

(52) Cache miss hit (lock bit is locked) In this case, depending on the state of the lock bit 40, a cache bypass write or a cache write
An allocation is determined. Then, in the locked state, data is written directly to the main storage device 50, bypassing the cache memory 30 (FIG. 5B). At this time, the lock bit 40 remains in the locked state, and the state of the dirty bit 41 remains as it was before execution (cache
Bypass write operation).

(53) Cache miss hit (lock bit is free, dirty bit is clean) In this case, since the lock bit is free, the cache directory 37 is replaced. The operation differs depending on the state of the dirty bit 41.
If it is in the clean state, the cache memory 30
At the same time as writing data directly to the cache directory 37 (FIG. 5C). At this time, the lock bit 40 is in the free state and the dirty bit 41 is
Becomes dirty (cache write allocate operation).

(54) Cache miss hit (lock bit is in free state, dirty bit is in dirty state) In this case, since the dirty bit 41 is in a dirty state, before replacing the cache directory 37, The data of the registered cache line is written back to the main storage device 50 (write-back operation). Next, data is directly written into the cache memory 30 and the cache directory 37 is re-registered at the same time (cache write allocate operation). At this time, the lock bit 40 is in the free state, and the dirty bit 41 is in the dirty state (FIG. 5D).

Next, a normal read operation will be described with reference to FIG. The operation in this case includes the following (61) to (6)
4). (61) Cache Hit In this case, data is directly read from the cache memory 30 (cache data read operation). At this time, the lock bit 40 and the dirty bit 41 remain the same as before execution (FIG. 6).
(A)).

(62) Cache Miss Hit (Lock Bit is Locked) In this case, cache bypass read or cache read replacement is determined by the state of lock bit 40. When the lock bit 40 is in the locked state, a cache bypass read operation is performed, and data is read from the main storage device 50 by bypassing the cache memory 30 (FIG. 6).
(B)). At this time, the lock bit 40 is in the locked state, and the dirty bit 41 is in the same state as before.

(63) Cache miss hit (lock bit is free, dirty bit is clean) In this case, the cache directory 37 is replaced, but the operation differs depending on the state of the dirty bit 41. . If the dirty bit 41 is in a clean state, the data is read from the main storage device 50 and simultaneously written into the cache memory 30, and the cache directory 37 is re-registered (cache directory).
Read replace operation). At this time, the lock bit 40 is in a free state, and the dirty bit 41 is in a clean state (FIG. 6C).

(64) Cache miss hit (lock bit is free, dirty bit is dirty) In this case, before replacing the cache directory 37, the data of the currently registered cache line is mainly The data is written back to the storage device 50 (write-back operation). Next, at the same time that data is read from the main storage device 50, writing is performed in the cache memory 30, and the cache directory 37 is re-registered (cache read / replace operation). At this time, the lock bit 40 is in the free state and the dirty bit 41 is in the clean state (FIG. 6D).

Next, a write operation with a lock instruction will be described with reference to FIG. The operation in this case is as follows (7)
1) to (75). (71) Cache hit (lock bit is locked) In this case, data is directly written to the cache memory 30 (cache data write operation). At this time, the lock bit 41 remains in the locked state, and the dirty bit 41 enters the dirty state (FIG. 7).
(A)).

(72) Cache hit (lock bit is in a free state) In this case, data is written directly to the cache memory 30 (cache data write operation). At this time, the lock bit 41 changes to the lock state, and the dirty bit 41 enters the dirty state (FIG. 7B).

(73) Cache miss hit (lock bit is locked) In this case, depending on the state of the lock bit, the cache
It is determined whether bypass write or cache write allocate is performed. Since the data is in the locked state, the data is written directly to the main storage device 50 bypassing the cache memory 30 (cache bypass write operation). At this time, the lock bit 40 remains locked and the dirty bit 41 remains as before (FIG. 7).
(C)).

(74) Cache miss hit (lock bit is free, dirty bit is clean) In this case, the cache directory 37 is replaced, but the operation differs depending on the state of the dirty bit 41. . In the clean state, data is written directly to the cache memory 30 and the cache directory 37 is re-registered at the same time (FIG. 7).
(D)). At this time, the lock bit 40 changes to the lock state, and the dirty bit 41 enters the dirty state (cache write allocate operation).

(75) Cache miss hit (lock bit is free, dirty bit is dirty) In this case, before replacing the cache directory 37, the data of the currently registered cache line is mainly The data is written back to the storage device 50 (write-back operation). Next, at the same time as the data is directly written to the cache memory 30, the cache directory 37 is re-registered (FIG. 7E). At this time, the lock bit 40 changes to the lock state, and the dirty bit 41 enters the dirty state (cache write allocate operation).

Next, a read operation with a free instruction will be described in the following (81) to (85) with reference to FIG. (81) Cache hit (lock bit is locked) In this case, data is directly read from the cache memory 30 (cache data read operation). At this time, the lock bit 40 changes to the free state, and the dirty bit 41 remains as it was before execution (FIG. 8).
(A)).

(82) Cache hit (lock bit is free) In this case, data is directly read from the cache memory 30 (cache data read operation). At this time, the lock bit 40 remains in the free state, and the dirty bit 41 remains as it was before execution (FIG. 8B).

(83) Cache Miss Hit (Lock Bit is Locked) In this case, the state of lock bit 40 determines cache bypass read / cache read replace. In this case, since it is in the locked state, the data is read from the main storage device 50 bypassing the cache memory 30 (FIG. 8C). At this time,
Bit 40 is locked and dirty bit 41 remains as it was before execution (cache bypass read operation).

(84) Cache miss hit (lock bit is locked, dirty bit is clean) In this case, the cache directory 37 is replaced, but the operation differs depending on the state of the dirty bit 41. . In the clean state, data is read from the main storage device 50 and the cache memory 30
And the cache directory 37 is re-registered (cache read / replace operation). At this time, the lock bit 40 is in the free state, and the dirty bit 41 is in the clean state (FIG. 8).
(D)).

(85) Cache Miss Hit (Lock Bit is Locked, Dirty Bit is Dirty) In this case, before replacing the cache directory 37, the data of the currently registered cache line is mainly The data is written back to the storage device 50 (write-back operation). Next, at the same time as the data is read from the main storage device 50, the data is also written to the cache memory 30 and the cache directory 37 is re-registered (cache read / replace operation). At this time, the lock bit 40 is in a free state, and the dirty bit 41 is in a clean state (FIG. 8E).

Referring to FIG. 9, the operation in the case where a write access to the same cache line by another address is executed between the stacking and drawing of the stack will be described with reference to the following (91) to (93). ). (91) Stacking (assuming a cache hit) In this case, the stack is directly stacked on the cache memory (cache data write). At this time, since the write with the lock instruction is performed, the lock bit is locked and the dirty bit is dirty (FIG. 9A).

(92) Write to the same cache line by another address In this case, this access is a cache miss hit, but since it is in a locked state, replacement of the cache directory is prohibited, and the cache memory is bypassed. The data is written directly to the main storage device 50 (cache
Bypass light). At this time, both the lock bit and the dirty bit remain as they were before execution (FIG. 9).
(B)).

(93) Extraction from Stack In this case, since the cache directory is protected by the lock state, this access becomes a cache hit. Stack data is directly extracted from the cache memory (cache data read). At this time, since the read with the free instruction is performed, the lock bit changes to the free state, and the cache directory can be replaced. The dirty bit remains in the dirty state (FIG. 9C).

In the present embodiment configured as described above, since the conventional double write-back operation as shown in FIG. 14 is not performed, the operation of writing back to the main storage device is reduced accordingly. However, as a result of the number of accesses to the main storage device of the processor being reduced, the average access time of the processor is reduced. In addition, the processing capability of the processor is improved, and the cache hit ratio is improved. For example, if the ratio of cache hit to access time per cache line is 1 clock to 5 clocks,
In the past, 17 clocks were used instead of 7 clocks (1 + 5
+1).

In the bypass access shown in FIG. 9B, the access for the bus width is performed only once, and the access is completed in a fixed time even if the cache line size is large. Therefore, the cache line size is large. Is particularly effective in this case, and the effect of reducing the access time is great.

Further, when the stacks are stacked, they are always pulled out within a short time. As described above, when the stacking is performed, the writing with the lock instruction is performed, and when the drawing is performed, the reading with the free instruction is performed. As a result, the use efficiency of the cache memory increases.

Further, with respect to frequently accessed data, it is possible to prevent the data from being evicted from the cache memory by a write instruction with a lock instruction, and since the data always exists in the cache memory, the main memory The number of accesses to the device is reduced. As a result, unnecessary replacement of the cache directory is prevented, and the number of write-back operations to the main storage device can be reduced.

[0073]

According to the present invention, it is possible to provide a cache memory device capable of improving the cache hit rate, reducing the number of accesses to the main storage device, and improving the processing performance.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a cache memory device according to an embodiment of the present invention.

2A is an explanatory diagram of a process when stacking is performed in the cache memory device of FIG. 1, and FIG. 2B is an explanatory diagram of a process when a stack is pulled out;

FIG. 3 is a block diagram of a lock memory in the cache memory device of FIG.
FIG. 7 is an explanatory diagram of bit state transitions.

FIG. 4 is a table illustrating an operation of the cache memory device of FIG. 1;

5 (a) to 5 (d) are explanatory diagrams of respective processes during a normal write operation in the cache memory device of FIG. 1;

6 (a) to 6 (d) are explanatory diagrams of respective processes during a normal read operation in the cache memory device of FIG. 1;

FIGS. 7A to 7E are explanatory diagrams of respective processes during a write operation with a lock instruction in the cache memory device of FIG. 1;

8 (a) to 8 (e) are explanatory diagrams of respective processes at the time of a read operation with a free instruction in the cache memory device of FIG. 1;

9 (a) to 9 (c) are explanatory diagrams of respective processes when a write access is executed between the time of stacking and the time of pulling out of the stack in the cache memory device of FIG. 1;

FIG. 10 is an explanatory diagram of a conventional cache memory device.

FIG. 11 is a chart for explaining the operation of the cache memory device of FIG. 10;

12 (a) to 12 (c) are explanatory diagrams of each processing at the time of a write operation in the cache memory of FIG. 10;

FIGS. 13A to 13C are explanatory diagrams of each processing at the time of a read operation in the cache memory device of FIG. 10;

14 (a) to (c) are explanatory diagrams of respective processes when cache write access is executed between the time of stacking and the time of pulling out of a stack in the cache memory device of FIG. 10;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Processor 11 Address control part 12 Lock instruction control part 13 Free instruction control part 16 Read / write control part 30 Cache memory 37 Cache directory 38 Tag data 39 Valid bit 40 Lock bit 41 Dirty bit 50 Main storage device

Claims (4)

[Claims] 1. A cache memory device of a write-back system provided between a processor and a main storage device, wherein at least one cache memory temporarily stores data read / written from the processor to the main storage device. A memory unit having two addresses; a memory management unit controlling read / write of data at each address of the memory unit; a locked state where data cannot be replaced at each address of the memory unit; and a free state where data can be replaced. A lock control unit to be set to any of the above, wherein the memory management unit, when a specific address of the memory unit is in a locked state, when the read / write access to this address from the processor, A cache miss where the data corresponding to this access does not exist at the address In the case of Tsu bets, the cache memory device, characterized in that to bypass the access to the main storage device. 2. The apparatus according to claim 1, wherein the lock control section shifts each address of the memory section from a free state to a locked state or from a locked state to a free state in accordance with an instruction from the processor. 2. The cache memory device according to 1. 3. The cache memory device according to claim 2, wherein a transition from a free state to a locked state of a specific address of said memory unit is performed when said address is written by said processor. 4. A transition from a locked state to a free state of a specific address of the memory section is performed when a cache hit in which data corresponding to a read access from the processor to the memory exists at this address. 3. The cache memory device according to claim 2, wherein said read operation is performed at the time of reading from said processor.